Patents by Inventor Chia-Kai Shih

Chia-Kai Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160233205
    Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.
    Type: Application
    Filed: April 20, 2016
    Publication date: August 11, 2016
    Inventors: Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Chi Hsu, Chia-Kai Shih, Shu-Huei Huang
  • Patent number: 9356008
    Abstract: A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: May 31, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Chia Chiang, Hsin-Ta Lin, Fu-Tang Huang, Yu-Po Wang, Lung-Yuan Wang, Chu-Chi Hsu, Chia-Kai Shih
  • Patent number: 9343421
    Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: May 17, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Chi Hsu, Chia-Kai Shih, Shu-Huei Huang
  • Patent number: 9343387
    Abstract: A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and an electronic element having a plurality of conductive posts, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, and each of the conductive posts and the corresponding conductive bump form a conductive element. The present invention facilitates the stacking process through butt joint of the conductive posts and the metal balls of the conductive bumps.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: May 17, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chu-Chi Hsu, Lung-Yuan Wang, Cheng-Chia Chiang, Chia-Kai Shih, Shu-Huei Huang
  • Publication number: 20160020195
    Abstract: A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.
    Type: Application
    Filed: February 6, 2015
    Publication date: January 21, 2016
    Inventors: Cheng-Chia Chiang, Hsin-Ta Lin, Fu-Tang Huang, Yu-Po Wang, Lung-Yuan Wang, Chu-Chi Hsu, Chia-Kai Shih
  • Publication number: 20150255360
    Abstract: A package on package (PoP) structure is provided, which includes: a packaging substrate having a plurality of conductive bumps, wherein each of the conductive bumps has a metal ball and a solder material covering the metal ball; and an electronic element having a plurality of conductive posts, wherein the electronic element is stacked on the packaging substrate by correspondingly bonding the conductive posts to the conductive bumps, and each of the conductive posts and the corresponding conductive bump form a conductive element. The present invention facilitates the stacking process through butt joint of the conductive posts and the metal balls of the conductive bumps.
    Type: Application
    Filed: August 6, 2014
    Publication date: September 10, 2015
    Inventors: Chu-Chi Hsu, Lung-Yuan Wang, Cheng-Chia Chiang, Chia-Kai Shih, Shu-Huei Huang
  • Publication number: 20150200169
    Abstract: A method for fabricating a semiconductor package is provided, which includes the steps of: providing a first substrate having a plurality of first conductive posts on a surface thereof and providing a second substrate having a third surface having a chip disposed thereon and a fourth surface opposite to the third surface; disposing the first substrate on the third surface of the second substrate through the first conductive posts; forming an encapsulant between the first substrate and the second substrate, wherein the encapsulant has a first surface adjacent to the first substrate and a second surface opposite to the first surface; and removing the first substrate, thereby effectively preventing solder bridging from occurring.
    Type: Application
    Filed: June 19, 2014
    Publication date: July 16, 2015
    Inventors: Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Chi Hsu, Chia-Kai Shih, Shu-Huei Huang
  • Publication number: 20150123287
    Abstract: A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a first substrate; disposing a second substrate on the first substrate through a plurality of supporting elements, wherein the second substrate has at least a cleaning hole penetrating therethrough; and performing a cleaning process to clean space between the second substrate and the first substrate through the cleaning hole, thereby preventing a popcorn effect from occurring when the first substrate is heated and hence preventing delamination of the semiconductor package. Further, the cleaning hole facilitates to disperse thermal stresses so as to prevent warping of the first and second substrates during a chip-bonding or encapsulating process, thereby overcoming the conventional drawbacks of cracking of the supporting elements and a short circuit therebetween.
    Type: Application
    Filed: December 19, 2013
    Publication date: May 7, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD
    Inventors: Chu-Chi Hsu, Lung-Yuan Wang, Cheng-Chia Chiang, Chia-Kai Shih
  • Publication number: 20150041972
    Abstract: A semiconductor package is disclosed, which includes: a first substrate; a first semiconductor component disposed on the first substrate; a second substrate disposed on the first semiconductor component and electrically connected to the first substrate through a plurality of conductive elements; and a first encapsulant formed between the first substrate and the second substrate and encapsulating the first semiconductor component and the conductive elements. The present invention can control the height and volume of the conductive elements since the distance between the first substrate and the second substrate is fixed by bonding the second substrate to the first semiconductor component.
    Type: Application
    Filed: April 10, 2014
    Publication date: February 12, 2015
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Kai Shih, Lung-Yuan Wang, Cheng-Chia Chiang, Chu-Chi Hsu, Shih-Hao Tung