Abstract: A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

Abstract: Embodiments include forming an interposer having reinforcing structures disposed in a core layer of the interposer. The interposer may be attached to a package device by electrical connectors. The reinforcing structures provide rigidity and thermal dissipation for the package device. Some embodiments may include an interposer with an opening in an upper core layer of the interposer to a recessed bond pad. Some embodiments may also use connectors between the interposer and the package device where a solder material connected to the interposer surrounds a metal pillar connected to the package device.

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.

Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

Abstract: Embodiments include forming an interposer having reinforcing structures disposed in a core layer of the interposer. The interposer may be attached to a package device by electrical connectors. The reinforcing structures provide rigidity and thermal dissipation for the package device. Some embodiments may include an interposer with an opening in an upper core layer of the interposer to a recessed bond pad. Some embodiments may also use connectors between the interposer and the package device where a solder material connected to the interposer surrounds a metal pillar connected to the package device.

Abstract: A clock generating device includes a divisor register, a reference clock generator, a first counter, a second counter, and a delay regulator circuit. The divisor register provides a divisor. The reference clock generator outputs a reference clock signal. The first counter counts a first number of cycles of the reference clock signal and generates a first count. The first counter outputs a first clock signal according to the first count and the divisor. The second counter counts a second number of cycles of the first clock signal and generates a second count. The second counter outputs a second clock signal according to the second count and a coefficient. The delay regulator circuit determines whether to control the first counter to delay outputting the first clock signal according to the first clock signal.

Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.