Abstract: The present disclosure describes a semiconductor device that includes a first die bonded to a second die with interconnect structures in the first die. The first die includes a photodiode having first and second electrodes on a first side of a first dielectric layer, and first, second, and third interconnect structures in the first dielectric layer. The first and second interconnect structures are connected to the first and second electrodes, respectively. The second electrode has a polarity opposite to the first electrode. The second and third interconnect structures extend to a second side opposite to the first side of the first dielectric layer. The second die includes a second dielectric layer and a fourth interconnect structure in the second dielectric layer. The second dielectric layer is bonded to the second side of the first dielectric layer. The fourth interconnect structure connects the second and third interconnect structures.

Abstract: A method of fabricating a semiconductor structure provided herein includes providing a thick-metal density range for a model structure, wherein the model structure includes a wafer substrate, and layers of metal patterns stacking on the wafer substrate; modifying the thick-metal density range to constrain a warpage range of the model structure toward a target range of warpage; and fabricating the semiconductor structure by forming the layers of metal patterns on the wafer substrate, wherein a thick-metal layer among the layers of metal patterns is formed based on the modified thick-metal density range, and a thickness of the thick-metal layer is twice or more of a thickness of one of the layers of metal patterns next to the thick-metal layer. A semiconductor structure fabricating by using the above method is further provided.

Abstract: A fabricating method of a middle voltage transistor includes providing a substrate. A gate predetermined region is defined on the substrate. Next, a mask layer is formed to cover only part of the gate predetermined region. Then, a first ion implantation process is performed to implant dopants into the substrate at two sides of the mask layer to form two first lightly doping regions. After removing the mask layer, a gate is formed to overlap the entirety gate predetermined region. Subsequently, two second lightly doping regions respectively formed within one of the first lightly doping regions. Next, two source/drain doping regions are respectively formed within one of the second lightly doping regions. Finally, two silicide layers are formed to respectively cover one of the source/drain doping regions.

Abstract: The present disclosure describes a semiconductor device that includes a first die bonded to a second die with interconnect structures in the first die. The first die includes a photodiode having first and second electrodes on a first side of a first dielectric layer, and first, second, and third interconnect structures in the first dielectric layer. The first and second interconnect structures are connected to the first and second electrodes, respectively. The second electrode has a polarity opposite to the first electrode. The second and third interconnect structures extend to a second side opposite to the first side of the first dielectric layer. The second die includes a second dielectric layer and a fourth interconnect structure in the second dielectric layer. The second dielectric layer is bonded to the second side of the first dielectric layer. The fourth interconnect structure connects the second and third interconnect structures.

Abstract: A method of fabricating a semiconductor device is provided. Recesses are formed in a substrate. A first gate dielectric material is formed on the substrate and filled in the recesses. The first gate dielectric material on the substrate between the recesses is at least partially removed to form a trench. A second gate dielectric material is formed in the trench. A gate conductive layer is formed on the second gate dielectric material. Spacers are formed on sidewalls of the gate conductive layer. A portion of the first gate dielectric material is removed. The remaining first gate dielectric material and the second gate dielectric layer form a gate dielectric layer. The gate dielectric layer includes a body part and a first hump part at a first edge of the body part. The first hump part is thicker than the body part. Doped regions are formed in the substrate beside the spacers.

Abstract: A semiconductor device includes a substrate; a channel region disposed in the substrate; and a diffusion region disposed in the substrate on a side of the channel region. The diffusion region comprises a LDD region and a heavily doped region within the LDD region. A gate electrode is disposed over the channel region. The gate electrode partially overlaps with the LDD region. A spacer is disposed on a sidewall of the gate electrode. A gate oxide layer is disposed between the gate electrode and the channel region, between the gate electrode and the LDD region, and between the spacer and the LDD region. A silicide layer is disposed on the heavily doped region and is spaced apart from the edge of the spacer.

Abstract: An idle time prediction method for a system includes obtaining n idle durations corresponding to n time points, determining if the n idle durations are of a normal distribution, generating a probability according to m idle states corresponding to m idle durations of the n idle durations if the n idle durations are not normally distributed, selecting a predicted idle state according to the probability, and controlling the system to enter the predicted idle state, where n and m are integers larger than one, and m?n.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a sensor semiconductor layer. The sensor semiconductor layer is doped with a first dopant. A photodetector is along a frontside of the sensor semiconductor layer. A backside semiconductor layer is along a backside of the sensor semiconductor layer, opposite the frontside. The backside semiconductor layer is doped with a second dopant. A diffusion barrier structure is between the sensor semiconductor layer and the backside semiconductor layer. The diffusion barrier structure includes a third dopant different from the first dopant and the second dopant.

Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate. A grid structure extends from a first side of the semiconductor substrate to within the semiconductor substrate. An image sensing element is disposed within the semiconductor substrate and is laterally surrounded by the grid structure. A plurality of protrusions are arranged along the first side of the semiconductor substrate. The plurality of protrusions are disposed over the image sensing element and are laterally surrounded by the grid structure. The plurality of protrusions are substantially identical to one another and have a characteristic dimension. An inner surface of the grid structure facing the image sensing element is spaced apart from a point of one of the plurality of protrusions by a predetermined reflective length that is based on the characteristic dimension of the plurality of protrusions.

Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate. A grid structure extends from a first side of the semiconductor substrate to within the semiconductor substrate. An image sensing element is disposed within the semiconductor substrate and is laterally surrounded by the grid structure. A plurality of protrusions are arranged along the first side of the semiconductor substrate. The plurality of protrusions are disposed over the image sensing element and are laterally surrounded by the grid structure. The plurality of protrusions are substantially identical to one another and have a characteristic dimension. An inner surface of the grid structure facing the image sensing element is spaced apart from a point of one of the plurality of protrusions by a predetermined reflective length that is based on the characteristic dimension of the plurality of protrusions.

Abstract: A pluggable optical packaging structure is provided, including: a substrate, a carrier ring, at least one optical connection assembly and a cover plate; the substrate includes at least one electronic integrated circuit (EIC) and at least one photonic integrated circuit (PIC); the carrier ring is located on the substrate, and the EIC and PIC are enclosed by the carrier ring; the optical connection assembly includes at least one socket, at least one connector, a plurality of optical fibers and at least one optical fiber array connector, the socket is located in a partial section of the carrier ring, the connector is in the socket, the optical fibers has one end coupled to the connector, the other end coupled to the fiber array connector, and is coupled to the PIC through the fiber array connector; the cover plate is located on the carrier ring and extends inwardly to above the PIC.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a plurality of semiconductor devices arranged on a substrate and within a device region. A first isolation structure is arranged in the device region and laterally between adjacent semiconductor devices in the plurality of semiconductor devices. An interconnect structure underlies the substrate and includes a topmost conductive interconnect element adjacent to the substrate. A second isolation structure is disposed in the substrate and around the device region. A bottom surface of the second isolation structure is above a lower surface of the topmost conductive interconnect element.

Abstract: Apparatuses and systems for stabilizing electron sources in charged particle beam inspection systems are provided. In some embodiments, a system may include an electron source comprising an emitting tip electrically connected to two electrodes and configured to emit an electron; and a base coupled to the emitting tip, wherein the base is configured to stabilize the emitting tip via the coupling.

Abstract: A transistor with an embedded insulating structure set includes a substrate. A gate is disposed on the substrate. A first lightly doped region is disposed at one side of the gate. A second lightly doped region is disposed at another side of the gate. The first lightly doped region and the second lightly doped region have the same conductive type. The first lightly doped region is symmetrical to the second lightly doped region. A first source/drain doped region is disposed within the first lightly doped region. A second source/drain doped region is disposed within the second lightly doped region. A first insulating structure set is disposed within the first lightly doped region and the first source/drain doped region. The first insulating structure set includes an insulating block embedded within the substrate. A sidewall of the insulating block contacts the gate dielectric layer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor device, the method including forming a plurality of photodetectors in a substrate. A device isolation structure is formed within the substrate. The device isolation structure laterally wraps around the plurality of photodetectors. An outer isolation structure is formed within the substrate. The device isolation structure is spaced between sidewalls of the outer isolation structure. The device isolation structure and the outer isolation structure comprise a dielectric material.

Abstract: An extended drain metal oxide semiconductor transistor includes a substrate. A gate is disposed on the substrate. A source doped region is disposed in the substrate at one side of the gate. A drain doped region is disposed in the substrate at another side of the gate. A thin gate dielectric layer is disposed under the gate. A thick gate dielectric layer is disposed under the gate. The thick gate dielectric layer extends from the bottom of the gate to contact the drain doped region. A second conductive type first well is disposed in the substrate and surrounds the source doped region and the drain doped region. A deep well is disposed within the substrate and surrounds the second conductive type first well.

Abstract: A high-voltage transistor includes a well region disposed in a semiconductor substrate, a gate structure disposed above the well region, a gate oxide layer disposed between the gate structure and the well region, a first drift region, and a second drift region. A first portion of the gate oxide layer is thicker than a second portion of the gate oxide layer. A thickness of the second portion is greater than or equal to one eighth of a thickness of the first portion. The first drift region and the second drift region are disposed in the well region, at least partially located at two opposite sides of the gate structure, respectively, and disposed adjacent to the first portion and the second portion, respectively. A conductivity type of the first drift region is identical to that of the second drift region. A level-up shifting circuit includes the high-voltage transistor described above.

Abstract: A semiconductor structure including a substrate and protection structures is provided. The substrate includes a die region. The die region includes corner regions. The protection structures are located in the corner region. Each of the protection structures has a square top-view pattern. The square top-view patterns located in the same corner region have various sizes.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor, and a method for forming the image sensor, in which an inter-pixel trench isolation structure is defined by a low-transmission layer. In some embodiments, the image sensor comprises an array of pixels and the inter-pixel trench isolation structure. The array of pixels is on a substrate, and the pixels of the array comprise individual photodetectors in the substrate. The inter-pixel trench isolation structure is in the substrate. Further, the inter-pixel trench isolation structure extends along boundaries of the pixels, and individually surrounds the photodetectors, to separate the photodetectors from each other. The inter-pixel trench isolation structure is defined by a low-transmission layer with low transmission for incident radiation, such that the inter-pixel trench isolation structure has low transmission for incident radiation.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor, and a method for forming the image sensor, in which an inter-pixel trench isolation structure is defined by a low-transmission layer. In some embodiments, the image sensor comprises an array of pixels and the inter-pixel trench isolation structure. The array of pixels is on a substrate, and the pixels of the array comprise individual photodetectors in the substrate. The inter-pixel trench isolation structure is in the substrate. Further, the inter-pixel trench isolation structure extends along boundaries of the pixels, and individually surrounds the photodetectors, to separate the photodetectors from each other. The inter-pixel trench isolation structure is defined by a low-transmission layer with low transmission for incident radiation, such that the inter-pixel trench isolation structure has low transmission for incident radiation.