Patents by Inventor Chia-Lan HSU

Chia-Lan HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11362094
    Abstract: A memory device and its manufacturing method are provided, including: a semiconductor substrate, including a shallow trench isolation structure and an active area positioned at one side of the shallow trench isolation structure; two buried word lines and a first dielectric layer, wherein the buried word lines are disposed in the semiconductor substrate and separated from each other, the first dielectric layer is disposed on the semiconductor substrate and corresponds to the two buried word lines; a contact plug disposed on the semiconductor substrate and within the active area, including a conductive layer and an epitaxial layer, the conductive layer is disposed on the sidewalls of the first dielectric layer, the epitaxial layer is disposed on the sidewalls of the conductive layer and extends into the semiconductor substrate; a second dielectric layer disposed over the semiconductor substrate, covering the contact plug and the shallow trench isolation structure.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: June 14, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Chia-Lan Hsu
  • Publication number: 20210183863
    Abstract: A memory device and its manufacturing method are provided, including: a semiconductor substrate, including a shallow trench isolation structure and an active area positioned at one side of the shallow trench isolation structure; two buried word lines and a first dielectric layer, wherein the buried word lines are disposed in the semiconductor substrate and separated from each other, the first dielectric layer is disposed on the semiconductor substrate and corresponds to the two buried word lines; a contact plug disposed on the semiconductor substrate and within the active area, including a conductive layer and an epitaxial layer, the conductive layer is disposed on the sidewalls of the first dielectric layer, the epitaxial layer is disposed on the sidewalls of the conductive layer and extends into the semiconductor substrate; a second dielectric layer disposed over the semiconductor substrate, covering the contact plug and the shallow trench isolation structure.
    Type: Application
    Filed: December 11, 2020
    Publication date: June 17, 2021
    Inventor: Chia-Lan HSU
  • Publication number: 20200185495
    Abstract: A semiconductor device is provided, including a substrate; a dielectric structure over the substrate; and a capping layer over the dielectric structure. The bottom of the capping layer has an M-shaped cross section. The capping layer and the dielectric structure are formed of different materials.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 11, 2020
    Inventors: Chien-Hsu TSENG, Chia-Lan HSU, Kai JEN, Yi-Hao CHIEN