Patents by Inventor Chia-Liang (Leon) Lin
Chia-Liang (Leon) Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12126342Abstract: A method of phase detection includes receiving a reference clock and an input clock having a first input signal and a second input; sampling the first input signal and the second input signal into a first sample and a second sample; converting the first sample and the second sample into a first current and a second current; using a regulated current mirror to convert the first current into the third current; using a first current steering network to steer the second current into either a fourth current or a fifth current in accordance with a pulse signal; using a second current steering network to steer the third current into either a sixth current or a seventh current; connecting a lowpass filter to the output node to establish an output voltage and a lowpass-filtered voltage; and forcing the standby voltage to be equal to the lowpass-filtered voltage using a unity-gain buffer.Type: GrantFiled: June 13, 2023Date of Patent: October 22, 2024Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Chia-Liang (Leon) Lin
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Patent number: 12107547Abstract: A SSB (single sideband) mixer is configured to mix a first signal with a second signal, both the first signal and the second signal being a four-phase signal, and comprises eight gated inverters, each receiving a respective phase of the first signal and conditionally outputting a respective current in accordance with a control of a respective phase of the second signal, wherein currents output from the eight gated inverters are summed to establish a third signal that is a two-phase signal.Type: GrantFiled: July 29, 2022Date of Patent: October 1, 2024Assignee: Realtek Semiconductor Corp.Inventor: Chia-Liang (Leon) Lin
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Publication number: 20240313726Abstract: A method of envelope detection operates by receiving a RF (radio frequency) signal having a first voltage at a first node and a second voltage at a second node; using a common-mode source-follower (CMSF) having a first source follower and a second source follower connected in parallel and configured to receive the first voltage and the second voltage, respectively, and jointly output a first current to a third node in accordance with a sum of a second current and a third current received via a fourth node; establishing a first negative feedback control loop by converting the first current into the third current using a current-controlled current source (CCCS); and establishing a second negative feedback control loop by converting a drain voltage at the third node into the second current using a voltage-controlled current source (VCCS).Type: ApplicationFiled: March 15, 2023Publication date: September 19, 2024Inventors: Chia-Liang (Leon) Lin, Ting-Hsu Chien
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Publication number: 20240313721Abstract: A method operates by receiving an input signal; transforming the input signal into a first transformed signal of a common-mode voltage equal to a first bias voltage; transforming the input signal into a second transformed signal of a common-mode voltage equal to a second bias voltage; detecting a peak of the first transformed signal and making the first bias voltage equal to a sum of a first DC (direct current) voltage and a first dynamic voltage; detecting a valley of the second transformed signal and making the second bias voltage equal to a sum of a second DC voltage and a second dynamic voltage; amplifying the first transformed signal into a first output signal across a first load using a N-type cascode amplifier; and amplifying the second transformed signal into a second output signal across a second load using a P-type cascode amplifier.Type: ApplicationFiled: March 13, 2023Publication date: September 19, 2024Inventor: Chia-Liang (Leon) Lin
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Publication number: 20240283480Abstract: A radio frequency integrated circuit (RFIC) includes a transmitter, a receiver, a first pin electrically shorted to a first node wherein the transmitter and the receiver are connected, and a second pin electrically shorted to a second node within the receiver. The RFIC is soldered on a printed circuit board (PCB). In a transmitter-receiver co-share configuration, the first pin is terminated with a high-impedance component on the PCB. In a transmitter-receiver split configuration, the first pin and the second pin are coupled through an external capacitor on the PCB.Type: ApplicationFiled: February 22, 2023Publication date: August 22, 2024Inventors: Ahmed Kord, Chia-Liang (Leon) Lin
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Patent number: 12052005Abstract: A transconductance amplifier includes a first MOS transistor configured to receive a first voltage at a first node and output a first current to a fifth node in accordance with a third voltage at a third node; a second MOS transistor configured to receive a second voltage at a second node and output a second current to a sixth node in accordance with a fourth voltage at a fourth node; a third MOS transistor configured to output a third current to the third node in accordance with a fifth voltage at the fifth node; a fourth MOS transistor configured to output a fourth current to the fourth node in accordance with a sixth voltage at the sixth node; and a source degeneration network placed across the third node and the fourth node.Type: GrantFiled: April 8, 2022Date of Patent: July 30, 2024Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Chia-Liang (Leon) Lin
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Publication number: 20240171142Abstract: A method operates to bias an RF receiver by incorporating a first NMOSFET as a common-source amplifier; incorporating a second NMOSFET as a cascode device stacked upon the first NMOSFET, injecting a reference current into a drain of a third NMOSFET; using a first operational amplifier to generate a first bias voltage to control a gate of the first NMOSFET, a gate of the third NMOSFET, and a gate of a fourth NMOSFET in accordance with a voltage difference between the drain of the third NMOSFET and a drain of the fourth NMOSFET; incorporating a fifth NMOSFET stacked upon the fourth NMOSFET; and using a second operational amplifier to generate a second bias voltage to control a gate of the second NMOSFET and a gate of the fifth NMOSFET in accordance with a voltage difference between a reference voltage and the drain of the fourth NMOSFET.Type: ApplicationFiled: November 21, 2022Publication date: May 23, 2024Inventors: Ahmed Kord, Chia-Liang (Leon) Lin
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Publication number: 20240162863Abstract: A method of envelope detection receives an RF (radio frequency) signal comprising a first voltage and a second voltage; converts the first voltage into a first current using a first VCCS (voltage controlled current source); converts the second voltage into a second current using a second VCCS; converts a bias voltage into a third current using a third VCCS; converting an output voltage into a fourth current using a fourth VCCS; sums the first current and the second current into an input current flowing through a first internal node of a first internal voltage; sums the third current and the fourth current into a mirrored current flowing through a second internal node of a second internal voltage; uses a source follower to receive the second internal voltage and output the output voltage; and uses a current mirror to force the mirrored current to be equal to the input current.Type: ApplicationFiled: November 10, 2022Publication date: May 16, 2024Inventor: Chia-Liang (Leon) Lin
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Publication number: 20240120906Abstract: A method of duty cycle adjustment includes conditionally inverting an input clock into a conditionally inverted clock; and adjusting a duty cycle of the conditionally inverted clock in one direction in accordance with an integer that represents an amount of duty cycle adjustment, using an uneven clock buffer and a plurality of uneven clock multiplexers that are cascaded and incrementally activated as a value of the integer increments.Type: ApplicationFiled: October 6, 2022Publication date: April 11, 2024Inventor: Chia-Liang (Leon) Lin
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Patent number: 11949376Abstract: A VCO (voltage-controlled oscillator) includes: a resonant tank having a parallel connection of an inductor, a fixed capacitor, a variable capacitor, a first temperature compensating capacitor, and a second temperature compensating capacitor across a first node and a second node, and configured to establish an oscillation of a first oscillatory voltage at the first node and a second oscillatory voltage at the second node; and a regenerative network placed across the first node and the second node to provide energy to sustain the oscillation. The variable capacitor is controlled by a control voltage, the first temperature compensating capacitor is controlled by a first temperature tracking voltage of a positive temperature coefficient, and the second temperature compensating capacitor is controlled by a second temperature tracking voltage of a negative temperature coefficient.Type: GrantFiled: November 9, 2021Date of Patent: April 2, 2024Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: I-Chang Wu, Chia-Liang (Leon) Lin
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Patent number: 11942943Abstract: A method of duty cycle adjustment includes conditionally inverting an input clock into a conditionally inverted clock; and adjusting a duty cycle of the conditionally inverted clock in one direction in accordance with an integer that represents an amount of duty cycle adjustment, using an uneven clock buffer and a plurality of uneven clock multiplexers that are cascaded and incrementally activated as a value of the integer increments.Type: GrantFiled: October 6, 2022Date of Patent: March 26, 2024Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Chia-Liang (Leon) Lin
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Publication number: 20240097720Abstract: A self-loopback radio transmitter having a transmitter with a modulator configured to up-convert a first baseband signal into a first RF (radio frequency) signal in accordance with a first LO (local oscillator) signal, and a power amplifier configured to receive the first RF signal and output a second RF signal to be emitted by an antenna and a third RF signal to be looped back, wherein the third RF signal is magnetically coupled from the second RF signal; and a loopback network having a shielded serial inductor configured to receive the third RF signal and output a fourth RF signal, and a demodulator configured to down-convert the fourth RF signal into a second baseband signal in accordance with a second LO signal, wherein the shielded serial inductor has a serial inductor of spiral topology and a coil laid out on a lower metal layer.Type: ApplicationFiled: October 13, 2022Publication date: March 21, 2024Inventors: Chia-Liang (Leon) Lin, Ting-Hsu Chien
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Publication number: 20240039476Abstract: A SSB (single sideband) mixer is configured to mix a first signal with a second signal, both the first signal and the second signal being a four-phase signal, and comprises eight gated inverters, each receiving a respective phase of the first signal and conditionally outputting a respective current in accordance with a control of a respective phase of the second signal, wherein currents output from the eight gated inverters are summed to establish a third signal that is a two-phase signal.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Inventor: Chia-Liang (Leon) Lin
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Publication number: 20230327620Abstract: A transconductance amplifier includes a first MOS transistor configured to receive a first voltage at a first node and output a first current to a fifth node in accordance with a third voltage at a third node; a second MOS transistor configured to receive a second voltage at a second node and output a second current to a sixth node in accordance with a fourth voltage at a fourth node; a third MOS transistor configured to output a third current to the third node in accordance with a fifth voltage at the fifth node; a fourth MOS transistor configured to output a fourth current to the fourth node in accordance with a sixth voltage at the sixth node; and a source degeneration network placed across the third node and the fourth node.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Inventor: Chia-Liang (Leon) Lin
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Publication number: 20230268899Abstract: A programmable gain amplifier includes a programmable resistor ladder deployed across Nmax junction nodes and controlled by Nmax?1 resistor control signals, where Nmax is an integer greater than one; a common-gate cascode amplifier multiplexer comprising Nmax common-gate cascode amplifiers configured to receive Nmax internal voltages at the Nmax junction nodes and output Nmax output currents in accordance with Nmax amplifier control signals, respectively, to an output node that is loaded with a load; and an AC (alternate current) coupling capacitor configured to couple an input node to the first junction node.Type: ApplicationFiled: February 18, 2022Publication date: August 24, 2023Inventor: Chia-Liang (Leon) Lin
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Patent number: 11728793Abstract: A four-stage gated ring oscillator having four gated amplifiers configured in a ring topology and comprising a first pair of gated amplifiers, controlled by a first phase of an two-phase input clock, interleaved with a second pair gated amplifiers, controlled by a second phase of the two-phase input clock; and two cross-coupling latches configured to provide cross-coupling between the first pair of gated amplifiers and the second pair of gated amplifiers.Type: GrantFiled: August 22, 2022Date of Patent: August 15, 2023Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Chia-Liang (Leon) Lin
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Patent number: 11720129Abstract: A voltage regulation system includes a voltage regulator configured to receive a first reference voltage and output a regulated voltage; a bias voltage generator comprising a diode-connect transistor configured to receive a bias current and output a reference gate voltage; and a plurality of switch-load circuits, each of said plurality of switch-load circuits comprising a common-drain transistor configured to receive power from the regulated voltage and control from the reference gate voltage via a switch controlled by a logical signal and output a supply voltage to load with a decoupling capacitor, wherein a size of the common-drain transistor is scaled from a size of the diode-connect transistor in accordance with a ratio between a current of the load and the bias current.Type: GrantFiled: April 27, 2020Date of Patent: August 8, 2023Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Chia-Liang (Leon) Lin
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Patent number: 11716071Abstract: A N-path filter includes a plurality of switch-capacitor circuits controlled by a plurality of logical signals, respectively, and joined at a common shunt node, each of said switch-capacitor circuit comprising: a respective switch configured to controllably connect the common shunt node to a respective middle node in accordance with a respective logical signals among said plurality of logical signals; and a respective balanced MOS (metal oxide semiconductor) capacitor connected to the respective middle node, wherein the respective balanced MOS capacitor exhibits a capacitance at the respective middle node with reference to a power supply node and a ground node.Type: GrantFiled: December 2, 2021Date of Patent: August 1, 2023Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Serkan Sayilir, Poh-boon Leong, Chia-Liang (Leon) Lin
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Patent number: 11695596Abstract: A multi-level signal transmitter includes an encoder figured to receive an input data and output a plurality of logical signal sets, each of said plurality of logical signal sets comprising a plurality of logical signals; and a plurality of tree-structured drivers configured to receive said plurality of logical signal sets, respectively, and jointly establish an output voltage at an output node, wherein each of said tree-structure drivers comprises a plurality of inverters configured to receive said plurality of logical signals of its respective logical signal set and jointly establish a joint voltage at a bifurcation node via coupling to the bifurcation node through a plurality of first-level weighting resistors, and a second-level weighting resistor configured to couple the bifurcation node to the output node.Type: GrantFiled: April 19, 2021Date of Patent: July 4, 2023Assignee: REALTEK SEMICONDUCTOR CORP.Inventors: Ting-Hsu Chien, Chia-Liang (Leon) Lin
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Publication number: 20230179174Abstract: A N-path filter includes a plurality of switch-capacitor circuits controlled by a plurality of logical signals, respectively, and joined at a common shunt node, each of said switch-capacitor circuit comprising: a respective switch configured to controllably connect the common shunt node to a respective middle node in accordance with a respective logical signals among said plurality of logical signals; and a respective balanced MOS (metal oxide semiconductor) capacitor connected to the respective middle node, wherein the respective balanced MOS capacitor exhibits a capacitance at the respective middle node with reference to a power supply node and a ground node.Type: ApplicationFiled: December 2, 2021Publication date: June 8, 2023Inventors: Serkan Sayilir, Poh-boon Leong, Chia-Liang (Leon) Lin