Patents by Inventor Chia-Lin Hung

Chia-Lin Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8976290
    Abstract: A positionable mechanism includes a base unit, a frame unit, an optical image stabilizing (OIS) unit and a positioning unit. The frame unit and the OIS unit are mounted on the base unit. The frame unit is retractable with respect to the base unit between a storage position and a working position, and has a first surface. The OIS unit includes a movable carrier that has a second surface facing the first surface, an optical element that is mounted on the movable carrier, and a driving element that is operable to drive the movable carrier to move with respect to the base unit. The positioning unit is disposed between the first surface and the second surface, and is configured to position the movable carrier with respect to the frame unit when the frame unit is at the storage position.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Asia Optical International Ltd.
    Inventors: Tsung-Tse Chen, Chia-Lin Hung, Huo-Wang Chou
  • Patent number: 8643167
    Abstract: The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of mounting a plurality of first dice to a wafer by conducting a reflow process; and thinning the wafer from the backside surface of the wafer, thereby reducing manufacturing time and preventing warpage.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: February 4, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chia-Lin Hung, Jen-Chuan Chen, Hui-Shan Chang, Kuo-Pin Yang
  • Publication number: 20130175324
    Abstract: The present invention provides a method and a thermal compression head for flip chip bonding. The thermal compression head includes a main body and a contact portion. The main body has a main body opening. The contact portion has a contact surface and a plurality of openings. The openings communicate with the main body opening. When the contact surface of the contact portion is used to adsorb a chip, the contact surface of the chip has a plurality of adsorbed zones corresponding to the contact surface openings. After the chip is bonded to a substrate, the protrusions of the adsorbed zones are relatively slight. Therefore, the interconnection between the chip and the substrate is ensured.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 11, 2013
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hui-Shan Chang, Chia-Lin Hung, Chung Chieh Huang
  • Patent number: 8446000
    Abstract: A package process includes following steps. A circuit mother board comprising a plurality of circuit boards is disposed on a carrier. Semiconductor devices are provided, wherein each of the semiconductor devices has a top surface and a bottom surface opposite thereto. Each of the semiconductor devices has conductive vias each having a first end surface and a second end surface exposed by the bottom surface of the semiconductor device. The semiconductor devices are connected to the corresponding circuit boards through their conductive vias with their bottom surface facing the circuit mother board. An insulating paste is formed between each of the semiconductor devices and its corresponding circuit board. A protection layer is formed on the circuit mother board to cover the semiconductor devices. Then, the protection layer and the semiconductor devices are thinned to expose the first end surface of each of the conductive vias.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: May 21, 2013
    Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan, Hui-Shan Chang, Chia-Lin Hung
  • Publication number: 20130120599
    Abstract: A positionable mechanism includes a base unit, a frame unit, an optical image stabilizing (OIS) unit and a positioning unit. The frame unit and the OIS unit are mounted on the base unit. The frame unit is retractable with respect to the base unit between a storage position and a working position, and has a first surface. The OIS unit includes a movable carrier that has a second surface facing the first surface, an optical element that is mounted on the movable carrier, and a driving element that is operable to drive the movable carrier to move with respect to the base unit. The positioning unit is disposed between the first surface and the second surface, and is configured to position the movable carrier with respect to the frame unit when the frame unit is at the storage position.
    Type: Application
    Filed: September 12, 2012
    Publication date: May 16, 2013
    Inventors: Tsung-Tse Chen, Chia-Lin Hung, Huo-Wang Chou
  • Publication number: 20120175767
    Abstract: The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of mounting a plurality of first dice to a wafer by conducting a reflow process; and thinning the wafer from the backside surface of the wafer, thereby reducing manufacturing time and preventing warpage.
    Type: Application
    Filed: December 5, 2011
    Publication date: July 12, 2012
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Lin Hung, Jen-Chuan Chen, Hui-Shan Chang, Kuo-Pin Yang
  • Publication number: 20110300669
    Abstract: The present invention relates to a method for making chip assemblies, including the following steps of: (a) providing a tested upper wafer and at least one tested lower wafer; (b) sawing the at least one tested lower wafer to form a plurality of lower dice, the lower dice including a plurality of know good lower dice; (c) picking up and rearranging the know good lower dice on a carrier according to the wafer map of the upper wafer; (d) bonding the upper wafer and the carrier; (e) removing the carrier; and (f) proceeding sawing step. Whereby, the dice of the die assembly are both known good dice, thus the yield loss caused by the different yields between the upper wafer and the lower wafer will not occur.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 8, 2011
    Inventors: Chi-Chih Shen, Jen-Chuan Chen, Hui-Shan Chang, Chia-Lin Hung, Ying-Sheng Chuang
  • Publication number: 20110121442
    Abstract: A package process includes following steps. A circuit mother board comprising a plurality of circuit boards is disposed on a carrier. Semiconductor devices are provided, wherein each of the semiconductor devices has a top surface and a bottom surface opposite thereto. Each of the semiconductor devices has conductive vias each having a first end surface and a second end surface exposed by the bottom surface of the semiconductor device. The semiconductor devices are connected to the corresponding circuit boards through their conductive vias with their bottom surface facing the circuit mother board. An insulating paste is formed between each of the semiconductor devices and its corresponding circuit board. A protection layer is formed on the circuit mother board to cover the semiconductor devices. Then, the protection layer and the semiconductor devices are thinned to expose the first end surface of each of the conductive vias.
    Type: Application
    Filed: May 24, 2010
    Publication date: May 26, 2011
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan, Hui-Shan Chang, Chia-Lin Hung