Patents by Inventor Chia-Lin Ku

Chia-Lin Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070249121
    Abstract: A method of fabricating a non-volatile memory is provided. The method includes providing a substrate. Next, a tunneling oxide layer is formed on the substrate and a surface nitridation process is performed to nitridize the upper surface of the tunneling oxide layer. A plurality of nanocrystals is formed on the nitridized surface of the tunneling oxide layer. Next, the surfaces of the nanocrystals are nitridized. An oxide layer and a conductive layer are formed in sequence over the tunneling oxide layer to cover the nanocrystals. Due to the formation of high-density nanocrystals as a charge storage medium, the properties of the memory are enhanced.
    Type: Application
    Filed: July 13, 2006
    Publication date: October 25, 2007
    Inventors: Chien-Kang Kao, Chia-Ming Kuo, Chia-Lin Ku
  • Publication number: 20050060108
    Abstract: The present invention is a field-measuring system and method supported by a PDA (Personal Digital Assistant) at the control processing field, comprising: a plurality of energy converters for sensing the processing variables at the control processing field and outputting the electric signals in response to the processing variables; a processing controller with a multi-port input interface for receiving the electric signals, processing the electric signals based on a single-chip microprocessor, and outputting the digital data corresponding to the processing variables; a personal digital assistant (PDA) for executing a driver to receive the digital data, and displaying the messages related to the processing variables; and a communication interface circuit for transmitting the data to a PDA. The combination of a PDA with a communication protocol technique facilitates the establishment of a real-time system for data retrieval and monitoring at a control processing field.
    Type: Application
    Filed: February 19, 2004
    Publication date: March 17, 2005
    Applicant: Metal Industries Research & Development Centre
    Inventor: Chia-Lin Ku
  • Patent number: 6764962
    Abstract: A method for forming oxynitride layer. The method includes (a) providing a substrate and removing the native oxide layer; (b) forming a nitride layer on the substrate; (c) oxidizing the nitride layer to form an oxynitride layer; and (d) subjecting the oxynitride layer to in-situ annealing. This method inhibits the penetration of boron into the substrate thereby improving the performance of semiconductor devices and production yield.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: July 20, 2004
    Assignee: ProMOS Technologies, Inc.
    Inventors: Yung-Hsien Wu, Chia-Lin Ku
  • Publication number: 20040128033
    Abstract: The present invention provides a valve actuator with an embedded integrated chip. Said valve actuator can be connected directly to the Internet so as to achieve the object of dispersed controlling.
    Type: Application
    Filed: May 20, 2003
    Publication date: July 1, 2004
    Applicant: Metal Industries Research & Development Centre
    Inventors: Chia-Lin Ku, Chin-Shun Lin
  • Publication number: 20030077915
    Abstract: A method for forming oxynitride layer. The method includes (a) providing a substrate and removing the native oxide layer; (b) forming a nitride layer on the substrate; (c) oxidizing the nitride layer to form an oxynitride layer; and (d) subjecting the oxynitride layer to in-situ annealing.
    Type: Application
    Filed: June 5, 2002
    Publication date: April 24, 2003
    Inventors: Yung-Hsien Wu, Chia-Lin Ku
  • Publication number: 20030001243
    Abstract: A method for monitoring the uniformity or quality of ultra-thin silicon nitride film uses wet re-oxidation of thin nitride to monitor its thickness variation to evaluate its quality. For nitride films with similar thicknesses, thinner oxide implies superior quality of the original nitride film and vice versa. The method of the present invention extends the use of ellipsometer measurement tools to the sub 10 Å level.
    Type: Application
    Filed: June 19, 2001
    Publication date: January 2, 2003
    Inventors: Yung-Hsien Wu, Chung Pei Chao, Chia-Lin Ku
  • Patent number: 6323137
    Abstract: A method of forming an arsenic doped oxide layer in a process chamber is disclosed. The method comprises the steps of: setting the process chamber to a temperature of approximately 400-500° C. and a pressure of about 40-250 torr; flowing tetraethylorthosilicate (TEOS) into the process chamber; flowing triethylarsenate (TEAS or TEASAT) into the process chamber; and flowing ozone into the process chamber.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: November 27, 2001
    Assignee: ProMOS Technologies
    Inventors: Feng-Wei Ku, Chia-Lin Ku
  • Patent number: 6171764
    Abstract: This invention provides methods for reducing the intensity of reflected rays encountered during the process of photolithography. By reducing the intensity of reflected ray, the pattern distortions associated with the interference from secondary rays can be minimized. In addition, this method for reducing the intensity of reflected ray can also eliminate the footing effect of other known methods in which the dielectric ARC layer is first deposited on the underlying layer, followed by the subsequent photolithography process of coating exposing, and developing.
    Type: Grant
    Filed: August 22, 1998
    Date of Patent: January 9, 2001
    Inventors: Chia-Lin Ku, Wen-Ping Yen
  • Patent number: 6156597
    Abstract: A method of fabricating a semiconductor device is provided including the steps of:(a) forming one or more protrusions on a semiconductor surface,(b) forming a first O.sub.x /TEOS film on top and side surfaces of the protrusions and surface area portions of the semiconductor surface separating the protrusions from each other, if any, and(c) forming a second O.sub.3 /TEOS film on, and covering, the first film.Illustratively, the protrusions have nitride regions at their peaks. The first film can be a low pressure (e.g., 30-70 torr) O.sub.3 /TEOS film or a plasma enhanced chemical vapor deposition (PECVD) O.sub.2 /TEOS film. The second film is a high pressure (e.g., 200-600 torr) O.sub.3 /TEOS film.The high pressure O.sub.3 /TEOS film avoids all of the disadvantages of the prior art. The low pressure O.sub.3 /TEOS film or PECVD O.sub.2 /TEOS film covers the nitride region of the protrusion so that the high pressure O.sub.3 /TEOS film will continuously cover the entire structure with a uniform thickness.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: December 5, 2000
    Assignees: ProMOS Technologies, Inc., Mosel Vitelic, Inc., Siemens AG
    Inventors: Wen-Ping Yen, Chia-Lin Ku, Chong-Che Lee
  • Patent number: 5869406
    Abstract: A method of fabricating an integrated circuit device with a substantially uniform inter-layer dielectric layer. The method includes steps of providing a partially completed semiconductor wafer (400) where the partially completed semiconductor device has a first polysilicon layer (401) thereon. The method includes depositing a dielectric layer (405) overlying the polysilicon layer and portions of the partially completed semiconductor device at a pressure of about 1 atmosphere. A step of forming a second polysilicon layer overlying portions of the dielectric layer is also included. The dielectric layer depositing step includes combining an organic silane and an ozone at a concentration of 200 g/m.sup.3 and less.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: February 9, 1999
    Assignee: Mosel Vitelic, Inc.
    Inventors: Wen-Doe Su, Chia-Lin Ku