Patents by Inventor Chia-Ling Lee

Chia-Ling Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240134268
    Abstract: A mask for use in a semiconductor lithography process includes a substrate, a mask pattern disposed on the substrate, and a light absorbing border surrounding the mask pattern. The light absorbing border is inset from at least two edges of the substrate to define a peripheral region outside of the light absorbing border. In some designs, a first peripheral region extends from an outer perimeter of the light absorbing border to a first edge of the substrate, and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate, where the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Chien-Cheng Chen, Huan-Ling Lee, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee
  • Publication number: 20240124844
    Abstract: The present disclosure provides a method for preparing a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors, the composition prepared by the method, and use of the composition for treating arthritis. The composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 18, 2024
    Inventors: Chia-Hsin Lee, Po-Cheng Lin, Yong-Cheng Kao, Ming-Hsi Chuang, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Publication number: 20240117314
    Abstract: The present invention relates to a method for preparing a modified stem cell, including the following steps: a cell culture step: culturing stem cells in a first culture medium of a culture dish at a predetermined cell density, and removing the first culture medium after a first culture time to obtain a first cell intermediate; an activity stimulation step: preserving the first cell intermediate in a freezing container having a cell cryopreservation solution, and performing a constant temperature stimulation treatment or a variable temperature stimulation treatment for at least more than 1 day; and a product collection step: after completing the activity stimulation step, placing the freezing container in an environment at a thawing temperature for thawing, and then removing the cell cryopreservation solution to obtain the modified stem cell. The modified stem cell can release at least one or more of IL-4, IL-5, IL-13, G-CSF, Fractalkine, and EGF.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 11, 2024
    Inventors: Ruei-Yue Liang, Chia-Hsin Lee, Kai-Ling Zhang, Po-Cheng Lin, Ming-Hsi Chuang, Yu-Chen Tsai, Peggy Leh Jiunn Wong
  • Publication number: 20240115616
    Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 11, 2024
    Inventors: Po-Cheng Lin, Pi-Chun Huang, Zih-Han Hong, Ming-Hsi Chuang, Yi-Chun Lin, Chia-Hsin Lee, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Publication number: 20240120325
    Abstract: A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.
    Type: Application
    Filed: May 31, 2023
    Publication date: April 11, 2024
    Applicant: POWERTECH TECHNOLOGY INC.
    Inventors: Pei-chun TSAI, Hung-hsin HSU, Shang-yu CHANG CHIEN, Chia-ling LEE
  • Publication number: 20240120437
    Abstract: A manufacturing method for a LED is disclosed. The method includes: providing a substrate with an upper surface; preparing a plurality of LEDs on the upper surface; wherein the upper surface is divided into a plurality of zones, the plurality of LEDs composes a plurality of LED groups, and each of the LED group is disposed in one of the plurality of zones; preparing a testing circuit to electrically connecting the plurality of LEDs in one of the plurality of LED groups; testing the plurality of LEDs in the one of the plurality of LED groups by the testing circuit to obtain photoelectrical characteristics of the plurality of LEDs in the one of the plurality of LED groups; and presenting the photoelectric characteristics in an image.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 11, 2024
    Inventors: Chia-Chen TSAI, Jia-Liang TU, Chi-Ling LEE
  • Publication number: 20240075071
    Abstract: Disclosed in the present invention is an optimized cell transplant. The optimized cell transplant is formed by performing gene induction and modification on a mesenchymal stem cell in the form of a small molecule and protein composition. The expression levels of CD200 gene, Galectin-9 gene and VISTA gene can be increased synchronously after cell culture. Vector virus infection and plasmid transfection are not required in the cell preparation process, so that high biological safety and great clinical application value of cells are achieved.
    Type: Application
    Filed: November 23, 2022
    Publication date: March 7, 2024
    Inventors: Ruei-Yue Liang, Kai-Ling Zhang, Ming-Hsi Chuang, Po-Cheng Lin, Peggy Leh Jiunn Wong, Chia-Hsin Lee
  • Patent number: 11916314
    Abstract: A mobile device includes a housing, a first radiation element, a second radiation element, a third radiation element, a first switch element, and a second switch element. The first radiation element has a first feeding point. The second radiation element has a second feeding point. The first radiation element, the second radiation element, and the third radiation element are distributed over the housing. The first switch element is closed or open, so as to selectively couple the first radiation element to the third radiation element. The second switch element is closed or open, so as to selectively couple the second radiation element to the third radiation element. An antenna structure is formed by the first radiation element, the second radiation element, and the third radiation element.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: February 27, 2024
    Assignee: HTC Corporation
    Inventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
  • Publication number: 20240021637
    Abstract: An image sensor package with low light-sensing noise has a chip body having a photosensitive area and non-sensitive area. The photosensitive area includes a photosensitive layer having a plurality of photosensitive units. A color filter is disposed on the photosensitive layer and has a plurality of filter units corresponding to the photosensitive units and a black matrix. A black adhesive layer is disposed on the non-sensitive area for mounting a glass cover. A gap is kept between the glass cover and the first surface of the chip body. When an incident light passes through the glass cover and emits to the photosensitive area, the black matrix absorbs the light traveling through the filter unit toward the photosensitive units adjacent to the filter unit. Furthermore, a light emitting to the non-sensitive area can be absorbed by the black adhesive layer. Thus, a light-sensing noise of the chip can be effectively decreased.
    Type: Application
    Filed: January 3, 2023
    Publication date: January 18, 2024
    Applicant: Powertech Technology Inc.
    Inventors: Wei-Lun HO, Chia-Ling LEE
  • Patent number: 11360524
    Abstract: An electronic device includes a first body, a second body, two hinges, and at least one electronic assembly. The two hinges are connected between the first body and the second body, and the first body and the second body are adapted to rotate relatively through the two hinges. The electronic assembly is connected to the second body and is located between the two hinges.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 14, 2022
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Chung Peng, Ko-Fan Chen, Chun-Yi Ho, Chien-Ting Lin, Yu-Jung Liu, Hsin-Jung Lee, Hsin-Yu Huang, Jih-Houng Lee, Ming-Feng Liu, Kuo-Jung Wu, Kuo-Pin Chen, Chia-Ling Lee, Jing-Jie Lin
  • Publication number: 20210157369
    Abstract: An electronic device includes a first body, a second body, two hinges, and at least one electronic assembly. The two hinges are connected between the first body and the second body, and the first body and the second body are adapted to rotate relatively through the two hinges. The electronic assembly is connected to the second body and is located between the two hinges.
    Type: Application
    Filed: February 4, 2021
    Publication date: May 27, 2021
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Chung Peng, Ko-Fan Chen, Chun-Yi Ho, Chien-Ting Lin, Yu-Jung Liu, Hsin-Jung Lee, Hsin-Yu Huang, Jih-Houng Lee, Ming-Feng Liu, Kuo-Jung Wu, Kuo-Pin Chen, Chia-Ling Lee, Jing-Jie Lin
  • Patent number: 10963019
    Abstract: An electronic device includes a first body, a second body, two hinges, and at least one electronic assembly. The two hinges are connected between the first body and the second body, and the first body and the second body are adapted to rotate relatively through the two hinges. The electronic assembly is connected to the second body and is located between the two hinges.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: March 30, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Chung Peng, Ko-Fan Chen, Chun-Yi Ho, Chien-Ting Lin, Yu-Jung Liu, Hsin-Jung Lee, Hsin-Yu Huang, Jih-Houng Lee, Ming-Feng Liu, Kuo-Jung Wu, Kuo-Pin Chen, Chia-Ling Lee, Jing-Jie Lin
  • Publication number: 20200387200
    Abstract: An electronic device includes a first body, a second body, two hinges, and at least one electronic assembly. The two hinges are connected between the first body and the second body, and the first body and the second body are adapted to rotate relatively through the two hinges. The electronic assembly is connected to the second body and is located between the two hinges.
    Type: Application
    Filed: January 21, 2020
    Publication date: December 10, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Ming-Chung Peng, Ko-Fan Chen, Chun-Yi Ho, Chien-Ting Lin, Yu-Jung Liu, Hsin-Jung Lee, Hsin-Yu Huang, Jih-Houng Lee, Ming-Feng Liu, Kuo-Jung Wu, Kuo-Pin Chen, Chia-Ling Lee, Jing-Jie Lin
  • Publication number: 20190057920
    Abstract: A method for manufacturing a semiconductor package includes: (a) providing a package device, the package device comprising a substrate, a package body and a plurality of connecting elements, the substrate having a first surface, the package body being disposed adjacent to the first surface of the substrate, and the connecting elements being disposed adjacent to the first surface of the substrate and encapsulated by the package body; and (b) removing a portion of the package body along one or more machining paths to expose the connecting elements, wherein each machining path has one or more first paths passing over, between, or along a side of at least two connecting elements, wherein a portion of each of the at least two connecting elements is within the package body, and another portion of each of the at least two connecting elements protrudes from a surface of the package body.
    Type: Application
    Filed: October 24, 2018
    Publication date: February 21, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chia-Ling LEE, Ming-Wei SUN, Chin-An SU, Cheng-Hua LIU
  • Publication number: 20180366605
    Abstract: A solar power sunroof device having a low reflectance is for receiving and reflecting a solar ray and a visible ray. A substrate is illuminated by the solar ray. A front contact layer has a first upper connecting surface and a first lower connecting surface. The first upper connecting surface is connected to the substrate. A photoelectric conversion layer is connected between the first lower connecting surface and a back contact layer. A low reflective layer has a third upper connecting surface and a third lower connecting surface. The third upper connecting surface is connected to the back contact layer, and the third lower connecting surface has a visible light reflectance. The visible ray illuminates the third lower connecting surface of the low reflective layer, and the third lower connecting surface scatters or absorbs the visible ray so as to decrease the visible light reflectance.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 20, 2018
    Inventors: Yung-Lin CHEN, Jia-Ming LEE, Chia-Ling LEE, Cheng-Yi CHOU
  • Publication number: 20180062010
    Abstract: An arc-bending translucent assembly is disclosed in the present disclosure. The arc-bending translucent assembly includes a first substrate and a second substrate. The first substrate has a first thickness and a second thickness at two sides thereof. The first substrate further includes a first arc surface and a second arc surface, in which a third thickness exists between a first top of the first arc surface and a second top of the second arc surface. The third thickness is larger than the first thickness or the second thickness. The second substrate is bent and disposed close to the second arc surface of the first substrate.
    Type: Application
    Filed: August 30, 2017
    Publication date: March 1, 2018
    Inventors: Chia-Ling LEE, Yung-Lin CHEN, Jia-Ming LEE
  • Publication number: 20160379910
    Abstract: The present disclosure relates to a semiconductor package and a method for manufacturing the same. The semiconductor package includes a substrate, a package body and at least two connecting elements. The substrate has a first surface. The package body is disposed adjacent to the first surface of the substrate, and the package body defines a groove having a substantially flat bottom surface. The connecting elements are disposed adjacent to the first surface of the substrate. A portion of each of the connecting elements is within the package body, and another portion of each of the connecting elements protrudes from the substantially flat bottom surface of the groove.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 29, 2016
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Ling Lee, Ming-Wei Sun, Chin-An Su, Cheng-Hua Liu
  • Publication number: 20130333750
    Abstract: The present invention discloses a thin-film solar cell and the manufacturing method thereof. A thin-film solar cell includes a substrate, a P-type layer, an interface layer, an I-type amorphous silicon layer, an I-type absorbing layer, an N-type layer and an electrode layer. The P-type is disposed on the substrate. The interface layer is disposed on the P-type layer. The I-type amorphous silicon layer is disposed on the interface layer. The I-type absorbing layer is disposed on the I-type amorphous silicon layer. The N-type layer is disposed on the I-type absorbing layer. The electrode layer is disposed on the N-type layer. Wherein, the I-type absorbing layer is thicker than 20% the I-type amorphous silicon layer, and the interface layer is thinner than 20% of the I-type amorphous silicon layer.
    Type: Application
    Filed: March 19, 2013
    Publication date: December 19, 2013
    Applicant: NEXPOWER TECHNOLOGY CORPORATION
    Inventors: CHIA-LING LEE, CHIEN-CHUNG BI
  • Publication number: 20130139875
    Abstract: The present invention discloses a thin-film solar cell and a method for forming the same. The thin-film solar cell includes a substrate and a semiconductor layer containing a P-type crystalline silicon layer over the substrate, a first I-type crystalline silicon layer on the P-type crystalline silicon layer, a first N-type crystalline silicon layer on the first I-type crystalline silicon layer, a second I-type crystalline silicon layer on the first N-type crystalline silicon layer and a second N-type crystalline silicon layer on the second I-type crystalline silicon layer. Wherein, the semiconductor layer is formed with additional I-type and N-type crystalline silicon layers, thereby enhancing the photoelectric conversion efficiency of the thin-film solar cell.
    Type: Application
    Filed: February 27, 2012
    Publication date: June 6, 2013
    Inventors: Chia-Ling LEE, Chien-Chung BI
  • Patent number: 7511936
    Abstract: The disclosure generally relates to a method for method for plasma etching a substrate in a plasma reactor comprising positioning the substrate on an electrostatic chuck inside the plasma reactor; supplying a DC voltage to the chuck, the DC voltage forming an electrostatic charge buildup on the substrate; plasma etching the substrate; disconnecting the DC voltage to the chuck; and counteracting the electrostatic charge buildup on the substrate by discharging a varying RF signal within the chamber.
    Type: Grant
    Filed: June 19, 2006
    Date of Patent: March 31, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cuker Huang, Shing-Long Lee, Yi-Jou Lu, Chia-Ling Lee