Abstract: An antenna structure includes a first signal source, a second signal source, a first radiator, a second radiator, a third radiator, a first circuit, and a second circuit. The first signal source is used to generate a first wireless signal, and the second signal source is used to generate a second wireless signal. The first radiator is coupled to the first signal source to receive the first wireless signal, and the second radiator is coupled to the second signal source to receive the second wireless signal. The first circuit has a first end coupled to the third radiator and a second end coupled to the first radiator or the first signal source. The second circuit has a first end coupled to the third radiator and a second end coupled to the second radiator or the second signal source.

Abstract: The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.

Abstract: A communication device includes a nonconductive track, an antenna element, a first turning wheel, and a second turning wheel. The antenna element is disposed on the nonconductive track. The first turning wheel and the second turning wheel drive the nonconductive track according to a control signal, so as to adjust the position of the antenna element. The communication device provides an almost omnidirectional radiation pattern.

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A first trench isolation structure is disposed in the substrate between the first device region and the second device region. The first trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is lower than the second bottom surface. The first trench isolation structure includes a first top surface within the first device region and a second top surface within the second device region. The first top surface is coplanar with the second top surface.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.

Abstract: The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.

Abstract: Various methods, apparatuses/systems, and media for integrating data are provided. A processor implements a data processing framework configured to run native on a big data platform and abstracts data processing constructs to a user friendly template, thereby eliminating necessity of user initiated tasks of instantiating language level objects. The processor also implements a core set of data pipeline configurations on the template configured to initiate a chain of user defined data transformations. A receiver operatively connected with the processor via a communication network receives input of the chain of the user defined data transformations. The processor tests each transformation independently of each other and outputs data integration solutions on the big data platform based on a positive test result.

Abstract: Various methods, apparatuses/systems, and media for integrating data are provided. A processor implements a data processing framework configured to run native on a big data platform and abstracts data processing constructs to a user friendly template, thereby eliminating necessity of user initiated tasks of instantiating language level objects. The processor also implements a core set of data pipeline configurations on the template configured to initiate a chain of user defined data transformations. A receiver operatively connected with the processor via a communication network receives input of the chain of the user defined data transformations. The processor tests each transformation independently of each other and outputs data integration solutions on the big data platform based on a positive test result.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: A folding ball trolley having a minimized volume has a frame, a bag and multiple resilient elements. The frame has four stand rods, four top seats, four sliding seats, four wheels, four connecting rod assemblies and four mounting rods. The bag connects to the mounting rods, and the mounting rods pivotally connect to the stand rods. Accordingly, the mounting rods can be rotated relative to the stand rods, such that the mounting rods do not protrude upward to occupy too much space when the ball trolley is folded. Besides, the frame is braced by the resilient elements so a user does not have to stretch his hands between the rods when folding the ball trolley, thereby preventing the hands from being clamped.

Abstract: A folding ball trolley has a frame and a bag. The frame has two main rod assemblies and two connecting rod assemblies. When the folding ball trolley is expanded, the main rods and the connecting rods lean outward under gravity until the main rods brace the bag. The bag holds the main rods at a specific angle, and the main rods hold the connecting rods at a specific angle. The main rod assemblies and the connecting rod assemblies are connected into a rectangle, such that the frame is expanded horizontally when the rods are leant outward. Thus, the folding ball trolley can achieve auto expansion without any resilient element, and therefore a user does not have to resist the resilient force when folding. Besides, the amount of the rods is reduced to eight (four main rods and four connecting rods), which reduces the manufacturing cost and facilitates ease of assembly.

Abstract: A folding ball trolley having minimized volume has a frame, a bag and multiple resilient elements. The frame has four stand rods, four top seats, four sliding seats, four wheels, four connecting rod assemblies and four mounting rods. The bag connects to the mounting rods and the mounting rods pivotally connect to the stand rods. Accordingly, the mounting rods can be rotated relative to the stand rods such that the mounting rods do not protrude upward to occupy too much space when the ball trolley is folded. Besides, the frame is braced by the resilient elements so a user does not have to stretch his hands between the rods when folding the ball trolley, thereby preventing the hands from being clamped.