Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. A first semiconductor region of a first semiconductor material is formed over the substrate and adjacent a second semiconductor region of a second semiconductor material. The first and second semiconductor regions are crystalline. An etchant is selective to etch the first semiconductor region over the second semiconductor region. The entire first semiconductor region is implanted to form an amorphized semiconductor region. The amorphized semiconductor region is etched with the etchant using the second semiconductor region as a mask to remove the amorphized semiconductor region without removing the second semiconductor region.

Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Abstract: A method for selectively removing a tungsten-including layer includes: forming a tungsten-including layer which has a first portion and a second portion; performing a treatment on a surface region of the first portion of the tungsten-including layer so as to convert tungsten in the surface region into tungsten oxide; and partially removing the tungsten-including layer using an etchant which has a higher etching selectivity to tungsten than tungsten oxide such that the second portion of the tungsten-including layer is fully removed, and the first portion of the tungsten-including layer, having the tungsten oxide in the surface region, is at least partially retained.

Abstract: An organic interposer includes dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the dielectric material layers, and die-side bump structures located on a second side of the dielectric material layers. A gap region is present between a first area including first die-side bump structures and a second area including second die-side bump structures. Stress-relief line structures are located on, or within, the dielectric material layers within an area of the gap region in the plan view. Each stress-relief line structures may include straight line segments that laterally extend along a respective horizontal direction and is not electrically connected to the redistribution interconnect structures. The stress-relief line structures may include the same material as, or may include a different material from, a metallic material of the redistribution interconnect structures or bump structures that are located at a same level.

Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).

Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).

Abstract: Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.

Abstract: Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.

Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AIN).

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).

Abstract: Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.

Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.

Abstract: An enhancement mode field-effect transistor (E-FET) for high static performance is provided. A composite barrier layer comprises a lower barrier layer and an upper barrier layer. The upper barrier layer is arranged over the lower barrier layer and has a different polarization than the lower barrier layer. Further, the composite barrier layer comprises a gate opening. A channel layer is arranged under the composite barrier layer, such that a heterojunction is defined at an interface between the channel layer and the composite barrier layer. A gate dielectric layer is arranged over the composite barrier layer and within the gate opening. A gate electrode is arranged over the gate dielectric layer. A method for manufacturing the E-FET is also provided.