Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.

Abstract: A two-dimension (2D) and three-dimension (3D) switchable display device and display driving method thereof are provided. Each pixel unit of the 2D and 3D switchable display device includes a first sub-pixel, a second sub-pixel and a third sub-pixel. The first sub-pixel, driven by a first gate line, has a first sub-pixel voltage, and the third sub-pixel, driven by a second gate line, has a third sub-pixel voltage different from the first sub-pixel voltage. The charge of the second sub-pixel is shared by a first gate line of an adjacent pixel unit, and the second sub-pixel has a second sub-pixel voltage different from the first sub-pixel voltage and the third sub-pixel voltage. The first sub-pixel, the second sub-pixel and the third sub-pixel of the pixel unit can be driven in a pre-charge driving manner.

Abstract: A pixel circuit is provided. The pixel circuit is electrically coupled to a data line, a first scan line, and a second scan line. The pixel circuit includes a first pixel unit, a second pixel unit, and a third pixel unit. The first pixel unit is electrically coupled to the data line and the second scan line, to determine a first displayed gray scale of the first pixel unit. The second pixel unit is electrically coupled to the data line and the first scan line, to determine a second displayed gray scale of the second pixel unit. The third pixel unit is electrically coupled to the data line, the first scan line, and the second scan line, to determine a third displayed gray scale of the third pixel unit.

Abstract: A liquid crystal display includes a date line for transmitting a data signal, a first gate line for transmitting a first gate signal, a second gate line for transmitting a second gate signal, a first sub-pixel unit for being written to by a first sub-pixel voltage according to the data signal and the first gate signal, a second sub-pixel unit for being written to by a second sub-pixel voltage according to the data signal and the first gate signal, a third sub-pixel unit for being written to by a third sub-pixel voltage according to the data signal and the first gate signal, and a charge sharing control unit. The charge sharing control unit is utilized for controlling a charge sharing operation over the first and third sub-pixel units according to the second gate signal, thereby adjusting the first and third sub-pixel voltages.

Abstract: A driving method of a display panel is described. A display panel including a pixel array is provided. The pixel array includes N scan lines, M data lines, and a plurality of first pixel units and a plurality of second pixel units electrically connected to the scan lines and the data lines. When an image is displayed with a wide-viewing angle mode, a first scanning procedure is performed to sequentially scan the first scan line of the scan lines to the Nth scan line of the scan lines in order. When the image is displayed with a narrow-viewing angle mode, the second scanning procedure is performed to sequentially scan the Nth scan line of the scan lines to the first scan line of the scan lines in order.

Abstract: Pixel structural designs on a display panel are disclosed. Each pixel on the display panel includes a plurality of sub-pixels. The sub-pixels are arranged sequentially along a vertical direction and used for displaying different colors in a circle. The display panel in the disclosure can be switched between a two-dimensional mode and a three-dimensional mode. In the three-dimensional mode, parts of the sub-pixels are disabled for forming a shielding area. Other adjacent sub-pixels form a pixel displaying unit.

Abstract: A pixel includes sub-pixels each of which includes a first display region, a second display region, a third display region, a first capacitor, and a second capacitor. The first capacitor connects the second display region with the third display region. The second capacitor connects the first display region to the third display region via a switch. When the switch is activated, the potential of the third display region is decreased via the second capacitor, the potential of the first display region is increased via the second capacitor, and the potential of the second display region is decreased via the first capacitor. A display panel and driving method in a display panel are also disclosed herein.

Abstract: An array substrate and a pixel unit of a display panel include a plurality of subpixels arranged in a pixel array (N row*M column). Only one data line is disposed in a portion of two adjacent columns of subpixels in the pixel array, and two data lines are disposed in another portion of two adjacent columns of subpixels in the pixel array.

Abstract: A two-dimension (2D) and three-dimension (3D) switchable display device and display driving method thereof are provided. Each pixel unit of the 2D and 3D switchable display device includes a first sub-pixel, a second sub-pixel and a third sub-pixel. The first sub-pixel, driven by a first gate line, has a first sub-pixel voltage, and the third sub-pixel, driven by a second gate line, has a third sub-pixel voltage different from the first sub-pixel voltage. The charge of the second sub-pixel is shared by a first gate line of an adjacent pixel unit, and the second sub-pixel has a second sub-pixel voltage different from the first sub-pixel voltage and the third sub-pixel voltage. The first sub-pixel, the second sub-pixel and the third sub-pixel of the pixel unit can be driven in a pre-charge driving manner.

Abstract: An array substrate and a pixel unit of a display panel include a plurality of subpixels arranged in a pixel array (N row*M column). Only one data line is disposed in a portion of two adjacent columns of subpixels in the pixel array, and two data lines are disposed in another portion of two adjacent columns of subpixels in the pixel array.

Abstract: A pixel circuit is provided. The pixel circuit is electrically coupled to a data line, a first scan line, and a second scan line. The pixel circuit includes a first pixel unit, a second pixel unit, and a third pixel unit. The first pixel unit is electrically coupled to the data line and the second scan line, to determine a first displayed gray scale of the first pixel unit. The second pixel unit is electrically coupled to the data line and the first scan line, to determine a second displayed gray scale of the second pixel unit. The third pixel unit is electrically coupled to the data line, the first scan line, and the second scan line, to determine a third displayed gray scale of the third pixel unit.

Abstract: A pixel includes sub-pixels each of which includes a first display region, a second display region, a third display region, a first capacitor, and a second capacitor. The first capacitor connects the second display region with the third display region. The second capacitor connects the first display region to the third display region via a switch. When the switch is activated, the potential of the third display region is decreased via the second capacitor, the potential of the first display region is increased via the second capacitor, and the potential of the second display region is decreased via the first capacitor. A display panel and driving method in a display panel are also disclosed herein.

Abstract: A driving method of a display panel is described. A display panel including a pixel array is provided. The pixel array includes N scan lines, M data lines, and a plurality of first pixel units and a plurality of second pixel units electrically connected to the scan lines and the data lines. When an image is displayed with a wide-viewing angle mode, a first scanning procedure is performed to sequentially scan the first scan line of the scan lines to the Nth scan line of the scan lines in order. When the image is displayed with a narrow-viewing angle mode, the second scanning procedure is performed to sequentially scan the Nth scan line of the scan lines to the first scan line of the scan lines in order.

Abstract: A liquid crystal display includes a date line for transmitting a data signal, a first gate line for transmitting a first gate signal, a second gate line for transmitting a second gate signal, a first sub-pixel unit for being written to by a first sub-pixel voltage according to the data signal and the first gate signal, a second sub-pixel unit for being written to by a second sub-pixel voltage according to the data signal and the first gate signal, a third sub-pixel unit for being written to by a third sub-pixel voltage according to the data signal and the first gate signal, and a charge sharing control unit. The charge sharing control unit is utilized for controlling a charge sharing operation over the first and third sub-pixel units according to the second gate signal, thereby adjusting the first and third sub-pixel voltages.