Abstract: A physical unclonable function (PUF) generator including a substrate and semiconductor units is provided. Each of the semiconductor units includes an isolation structure, a first conductive line, and a second conductive line. The isolation structure is located in the substrate. The isolation structure has a first protrusion portion and a recess. The first protrusion portion and the recess are adjacent to each other. The first conductive line is located above the first protrusion portion and the recess. The second conductive line is located above the first conductive line. At least one short circuit randomly exists between at least one of the first conductive lines and at least one of the second conductive lines in at least one of the semiconductor units.

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

Abstract: The present invention provides a laterally diffused metal-oxide-semiconductor (LDMOS) transistor and a manufacturing method thereof. The LDMOS transistor includes a semiconductor substrate, an insulation structure, agate structure, and a plurality of floating electrodes. The insulation structure is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The floating electrodes are embedded in the insulation structure, wherein the floating electrode closest to the gate structure protrudes from a top surface of the insulation structure or the gate structure includes at least one branch portion embedded in the insulation structure, and the floating electrodes are separated from the gate structure.

Abstract: A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure.

Abstract: The present invention provides a laterally diffused metal-oxide-semiconductor (LDMOS) transistor and a manufacturing method thereof. The LDMOS transistor includes a semiconductor substrate, an insulation structure, agate structure, and a plurality of floating electrodes. The insulation structure is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The floating electrodes are embedded in the insulation structure, wherein the floating electrode closest to the gate structure protrudes from a top surface of the insulation structure or the gate structure includes at least one branch portion embedded in the insulation structure, and the floating electrodes are separated from the gate structure.

Abstract: A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure.

Abstract: A high-voltage metal-oxide-semiconductor (HV MOS) transistor device and a manufacturing method thereof are provided. The HV MOS transistor device includes a semiconductor substrate, a gate structure, a first sub-gate structure, and a drain region. The gate structure is disposed on the semiconductor substrate. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the semiconductor substrate, the first sub-gate structure is separated from the gate structure, and the first sub-gate structure is disposed on the first region of the semiconductor substrate. The drain region is disposed in the first region of the semiconductor substrate. The drain region is electrically connected to the first sub-gate structure via a first contact structure disposed on the drain region and the first sub-gate structure.