Patents by Inventor Chia-Ming Ho

Chia-Ming Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10140407
    Abstract: A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming Ho, Adari Rama Bhadra Rao, Meng-Kai Hsu, Kuang-Hung Chang, Ke-Ying Su, Wen-Hao Chen, Hsien-Hsin Sean Lee
  • Patent number: 10019548
    Abstract: A method, of generating a modified layout based on an original layout, includes: determining a first set of width bias values of an i-th set of layout patterns which compensate for subtractive process effects, the original layout having N sets of layout patterns corresponding to N masks; determining a second set of width bias values of the i-th set of layout patterns of the original layout which compensate for additive process effects; generating the modified layout based on the first and second sets of width bias values of the i-th set of layout patterns, the order index i of the i-th mask corresponding to an order of the i-th mask being applied during a fabrication process; and fabricating, based on the modified layout, at least one of a semiconductor mask or at least one component in a layer of an inchoate semiconductor integrated circuit.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: July 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming Ho, Ke-Ying Su, Hsien-Hsin Sean Lee
  • Patent number: 9922162
    Abstract: A method includes generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions includes a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a first spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the first spacing values.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming Ho, C. Y. (Chia-Yi) Chen, Hsiu-Wen Hsueh, Jun-Fu Huang, Shao-Heng Chou
  • Publication number: 20170316142
    Abstract: A method, of generating a modified layout based on an original layout, includes: determining a first set of width bias values of an i-th set of layout patterns which compensate for subtractive process effects, the original layout having N sets of layout patterns corresponding to N masks; determining a second set of width bias values of the i-th set of layout patterns of the original layout which compensate for additive process effects; generating the modified layout based on the first and second sets of width bias values of the i-th set of layout patterns, the order index i of the i-th mask corresponding to an order of the i-th mask being applied during a fabrication process; and fabricating, based on the modified layout, at least one of a semiconductor mask or at least one component in a layer of an inchoate semiconductor integrated circuit.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Chia-Ming HO, Ke-Ying SU, Hsien-Hsin Sean LEE
  • Patent number: 9710588
    Abstract: A method of includes determining a first set of width bias values of an i-th set of layout patterns of an original layout according a first type width variation. The original layout has N sets of layout patterns corresponding to N masks, where the i-th set of layout patterns has an i-th mask assignment corresponding to an i-th mask of the N masks. The order index i is an integer from 1 to N, and N is an integer and greater than 1. A second set of width bias values of the i-th set of layout patterns of the original layout is determined according to a second type width variation. The modified layout is generated based on the first and second sets of width bias values of the i-th set of layout patterns.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming Ho, Ke-Ying Su, Hsien-Hsin Sean Lee
  • Publication number: 20160147928
    Abstract: A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Inventors: Chia-Ming HO, Adari Rama Bhadra RAO, Meng-Kai HSU, Kuang-Hung CHANG, Ke-Ying SU, Wen-Hao CHEN, Hsien-Hsin Sean LEE
  • Publication number: 20160103948
    Abstract: A method includes generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions includes a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a first spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the first spacing values.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 14, 2016
    Inventors: Chia-Ming HO, C. Y. (Chia-Yi) CHEN, Hsiu-Wen HSUEH, Jun-Fu HUANG, Shao-Heng CHOU
  • Publication number: 20160042108
    Abstract: A method of includes determining a first set of width bias values of an i-th set of layout patterns of an original layout according a first type width variation. The original layout has N sets of layout patterns corresponding to N masks, where the i-th set of layout patterns has an i-th mask assignment corresponding to an i-th mask of the N masks. The order index i is an integer from 1 to N, and N is an integer and greater than 1. A second set of width bias values of the i-th set of layout patterns of the original layout is determined according to a second type width variation. The modified layout is generated based on the first and second sets of width bias values of the i-th set of layout patterns.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 11, 2016
    Inventors: Chia-Ming HO, Ke-Ying SU, Hsien-Hsin Sean LEE
  • Patent number: 9230052
    Abstract: A method of generating a simulation model of a predefined fabrication process according to a sample conductive feature includes receiving a geometry configuration and layout design of the conductive feature. A circuit-level simulation model of the sample conductive feature based on the geometry configuration of the sample conductive feature is generated. A hardware processor converts the circuit-level simulation model of the sample conductive feature into at least a first layout bias rule corresponding to a first set of predetermined criteria of the layout design and a second layout bias rule, different from the first layout bias rule, corresponding to a second set of predetermined criteria of the layout design.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: January 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming Ho, Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng
  • Patent number: 9218448
    Abstract: A method comprises generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions comprises a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the spacing values.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: December 22, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming Ho, C. Y. Chen, Hsiu-Wen Hsueh, Jun-Fu Huang, Shao-Heng Chou
  • Publication number: 20150205905
    Abstract: A method comprises generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions comprises a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the spacing values.
    Type: Application
    Filed: January 20, 2014
    Publication date: July 23, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming HO, C, Y. CHEN, Hsiu-Wen HSUEH, Jun-Fu HUANG, Shao-Heng CHOU
  • Publication number: 20150052493
    Abstract: A method of generating a simulation model of a predefined fabrication process according to a sample conductive feature includes receiving a geometry configuration and layout design of the conductive feature. A circuit-level simulation model of the sample conductive feature based on the geometry configuration of the sample conductive feature is generated. A hardware processor converts the circuit-level simulation model of the sample conductive feature into at least a first layout bias rule corresponding to a first set of predetermined criteria of the layout design and a second layout bias rule, different from the first layout bias rule, corresponding to a second set of predetermined criteria of the layout design.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 19, 2015
    Inventors: Chia-Ming HO, Ke-Ying SU, Hsiao-Shu CHAO, Yi-Kan CHENG
  • Patent number: 8954900
    Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ming Ho, Kun-Ting Tsai, Tsung-Han Wu, Ke-Ying Su, Hsien-Hsin Sean Lee
  • Publication number: 20150040077
    Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. The patterns are divided into first and second groups, to be patterned on the single layer by a first mask or a second mask. For each portion of each pattern, a spacing relationship is determined between that portion and any adjacent pattern on either or both sides. A processor computes a first capacitance (C), resistance (R), or resistance-capacitance (RC) cost of assigning the first group to the first mask and the second group to the second mask, and a second cost of assigning the first group to the second mask and the second group to the first mask, based on the spacing relationships. The first group is assigned to the first mask and the second group to the second mask if the first cost is lower than the second cost.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ming HO, Kun-Ting TSAI, Tsung-Han WU, Ke-Ying SU, Hsien-Hsin Sean LEE
  • Patent number: 8904314
    Abstract: Among other things, one or more systems and techniques for width bias adjustment for a design layout are provided. During fabrication, characteristics of a component can change, such as size, width, position, etc., from how a design layout represents such components. Accordingly, a width bias table is used to identify a width bias value that can be applied between a first polygon and a second polygon to compensate for a characteristic change associated with at least one of the first polygon and the second polygon during fabrication. The width bias value is used during RC extraction to determine an electrical characteristic adjustment, such as an additional capacitance or resistance associated with the width bias value, for at least one of the first polygon and the second polygon. In this way, RC extraction, during a design phase, can take into account electrical characteristic changes that occur during fabrication.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chia-Ming Ho, Te-Yu Liu, Ke-Ying Su, Hsien-Hsin Lee
  • Patent number: 8887116
    Abstract: The present disclosure relates to a method of RC extraction that provides for a fast development time and easy maintenance. In some embodiments, the method provides a graphical representation of an integrated chip layout having a plurality of integrated chip components. A plurality of pattern based graphical features are then determined. Respective pattern based graphical features define a structural aspect of an integrated chip component. One of the plurality of integrated chip components is defined as a pattern oriented function having inputs of one or more of the pattern based graphical features. The pattern oriented function determines a shape of the one of the plurality of integrated chip components based upon a relation between the plurality of inputs. By determining a shape of an integrated chip component using a pattern oriented function, the complexity of RC profiles can be reduced.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ming Ho, Te-Yu Liu, Austin Chingyu Chiang, Meng-Fan Wu, Ke-Ying Su
  • Patent number: 8887106
    Abstract: A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ming Ho, Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng
  • Publication number: 20140282341
    Abstract: The present disclosure relates to a method of RC extraction that provides for a fast development time and easy maintenance. In some embodiments, the method provides a graphical representation of an integrated chip layout having a plurality of integrated chip components. A plurality of pattern based graphical features are then determined. Respective pattern based graphical features define a structural aspect of an integrated chip component. One of the plurality of integrated chip components is defined as a pattern oriented function having inputs of one or more of the pattern based graphical features. The pattern oriented function determines a shape of the one of the plurality of integrated chip components based upon a relation between the plurality of inputs. By determining a shape of an integrated chip component using a pattern oriented function, the complexity of RC profiles can be reduced.
    Type: Application
    Filed: May 31, 2013
    Publication date: September 18, 2014
    Inventors: Chia-Ming Ho, Te-Yu Liu, Austin Chingyu Chiang, Meng-Fan Wu, Ke-Ying Su
  • Publication number: 20140258962
    Abstract: A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer.
    Type: Application
    Filed: April 30, 2013
    Publication date: September 11, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ming Ho, Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng, Ze-Ming Wu, Hsien-Hsin Sean Lee
  • Patent number: 8826213
    Abstract: A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ming Ho, Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng, Ze-Ming Wu, Hsien-Hsin Sean Lee