Patents by Inventor Chia-Ming Hung
Chia-Ming Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11937932Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.Type: GrantFiled: July 8, 2022Date of Patent: March 26, 2024Assignees: TAICHUNG VETERANS GENERAL HOSPITAL, TUNGHAI UNIVERSITYInventors: Chieh-Liang Wu, Chun-Te Huang, Cheng-Hsu Chen, Tsai-Jung Wang, Kai-Chih Pai, Chun-Ming Lai, Min-Shian Wang, Ruey-Kai Sheu, Lun-Chi Chen, Yan-Nan Lin, Chien-Lun Liao, Ta-Chun Hung, Chien-Chung Huang, Chia-Tien Hsu, Shang-Feng Tsai
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Patent number: 11851323Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A first cavity and a second cavity are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a first movable membrane overlying the first cavity and a second movable membrane overlying the second cavity. A first functional structure overlies the first movable membrane, where the first functional structure comprises a first material having a first chemical composition.Type: GrantFiled: June 22, 2020Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
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Publication number: 20230406695Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A first cavity and a second cavity are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a first movable membrane overlying the first cavity and a second movable membrane overlying the second cavity. A first functional structure overlies the first movable membrane, where the first functional structure comprises a first material having a first chemical composition.Type: ApplicationFiled: August 4, 2023Publication date: December 21, 2023Inventors: Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
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Patent number: 11834332Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.Type: GrantFiled: February 14, 2022Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kang-Yi Lien, Kuan-Chi Tsai, Yi-Chieh Huang, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
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Publication number: 20230382723Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Kang-Yi Lien, I-Hsuan Chiu, Yi-Chieh Huang, Chia-Ming Hung, Kuan-Chi Tsai, Hsiang-Fu Chen
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Publication number: 20230382724Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: Wen-Chuan Tai, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu, Fan Hu
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Publication number: 20230386948Abstract: A semiconductor device and method of forming such a device includes a MEMS component including one or more MEMS pixels and having a MEMS membrane substrate and a MEMS sidewall. The semiconductor device includes an analog circuit component bonded to the MEMS component, and which includes at least one analog CMOS component within an analog circuit insulative layer, and an analog circuit component substrate. The semiconductor device includes an HPC component bonded to the analog circuit component substrate. The HPC component includes at least one HPC metal component disposed within an HPC insulative layer, at least one bond pad, at least one bond pad via connecting the at least one bond pad and the at least one HPC metal component, and an HPC substrate. Additionally, the semiconductor device includes a DTC component bonded to the HPC substrate, and which includes a DTC die disposed in a DTC substrate.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Inventors: You-Ru Lin, Sheng Kai Yeh, Jen-Yuan Chang, Chi-Yuan Shih, Chia-Ming Hung, Hsiang-Fu Chen, Shih-Fen Huang
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Publication number: 20230282726Abstract: A semiconductor device includes a first substrate having opposite first and second sides, a first conductive layer on the first side of the first substrate, and a second substrate having opposite first and second sides. The second side of the second substrate is bonded to the first side of the first substrate. The second substrate includes a semiconductor material, and at least one circuit element electrically coupled to the first conductive layer. The at least one circuit element includes at least one of a Schottky diode configured by the semiconductor material and a first contact structure, a capacitor having a first electrode of the semiconductor material, or a resistor of the semiconductor material.Type: ApplicationFiled: June 14, 2022Publication date: September 7, 2023Inventors: Chia-Ming HUNG, I-Hsuan CHIU, Hsiang-Fu CHEN, Kang-Yi LIEN, Chu-Heng CHEN
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Publication number: 20230278073Abstract: A semiconductor device and method of manufacturing the same that utilizes dielectric pedestals on a sensing electrode. The semiconductor device includes a one or more membranes and an integrated circuit substrate. The integrated circuit substrate includes one or more conductive components disposed within a first dielectric layer on the substrate, with the conductive components interconnected with respective integrated circuit components. The substrate further includes one or more sensing electrodes electrically coupled to the conductive components, and one or more dielectric pedestals positioned within a landing area of the sensing electrode. In addition, the semiconductor device includes at least one cavity that is formed by the membrane positioned over the sensing electrode.Type: ApplicationFiled: March 7, 2022Publication date: September 7, 2023Inventors: Kang-Yi Lien, Kuan-Chi Tsai, Yi-Chieh Huang, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
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Publication number: 20230043571Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.Type: ApplicationFiled: February 14, 2022Publication date: February 9, 2023Inventors: Kang-Yi Lien, Kuan-Chi Tsai, Yi-Chieh Huang, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
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Publication number: 20220362804Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A plurality of cavities are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a plurality of movable membranes, and where the movable membranes overlie the cavities, respectively. A plurality of fluid communication channels are disposed in the dielectric structure, where each of the fluid communication channels extend laterally between two neighboring cavities of the cavities, such that each of the cavities are in fluid communication with one another.Type: ApplicationFiled: July 25, 2022Publication date: November 17, 2022Inventors: I-Hsuan Chiu, Chia-Ming Hung, Li-Chun Peng, Hsiang-Fu Chen
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Patent number: 11491510Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A plurality of cavities are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a plurality of movable membranes, and where the movable membranes overlie the cavities, respectively. A plurality of fluid communication channels are disposed in the dielectric structure, where each of the fluid communication channels extend laterally between two neighboring cavities of the cavities, such that each of the cavities are in fluid communication with one another.Type: GrantFiled: May 13, 2020Date of Patent: November 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Hsuan Chiu, Chia-Ming Hung, Li-Chun Peng, Hsiang-Fu Chen
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Publication number: 20220219973Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, where the method includes forming an interconnect structure over a first substrate. A dielectric structure is formed over the interconnect structure. The dielectric structure comprises opposing sidewalls defining an opening. A conductive bonding structure is formed on a second substrate. A bonding process is performed to bond the conductive bonding structure to the interconnect structure. The conductive bonding structure is disposed in the opening. The bonding process defines a first cavity between inner opposing sidewalls of the conductive bonding structure and a second cavity between the conducive bonding structure and the opposing sidewalls of the dielectric structure.Type: ApplicationFiled: March 29, 2022Publication date: July 14, 2022Inventors: Hung-Hua Lin, Chia-Ming Hung, Xin-Hua Huang, Yuan-Chih Hsieh
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Patent number: 11292715Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device including a conductive bonding structure disposed between a substrate and a MEMS substrate. An interconnect structure overlies the substrate. The MEMS substrate overlies the interconnect structure and includes a moveable membrane. A dielectric structure is disposed between the interconnect structure and the MEMS substrate. The conductive bonding structure is sandwiched between the interconnect structure and the MEMS substrate. The conductive bonding structure is spaced laterally between sidewalls of the dielectric structure. The conductive bonding structure, the MEMS substrate, and the interconnect structure at least partially define a cavity. The moveable membrane overlies the cavity and is spaced laterally between sidewalls of the conductive bonding structure.Type: GrantFiled: October 15, 2019Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Hua Lin, Chia-Ming Hung, Xin-Hua Huang, Yuan-Chih Hsieh
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Patent number: 10981781Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.Type: GrantFiled: November 4, 2019Date of Patent: April 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Chia-Ming Hung, Shao-Chi Yu, Hung-Hua Lin, Yuan-Chih Hsieh
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Publication number: 20210060610Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A plurality of cavities are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a plurality of movable membranes, and where the movable membranes overlie the cavities, respectively. A plurality of fluid communication channels are disposed in the dielectric structure, where each of the fluid communication channels extend laterally between two neighboring cavities of the cavities, such that each of the cavities are in fluid communication with one another.Type: ApplicationFiled: May 13, 2020Publication date: March 4, 2021Inventors: I-Hsuan Chiu, Chia-Ming Hung, Li-Chun Peng, Hsiang-Fu Chen
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Publication number: 20210061647Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A first cavity and a second cavity are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a first movable membrane overlying the first cavity and a second movable membrane overlying the second cavity. A first functional structure overlies the first movable membrane, where the first functional structure comprises a first material having a first chemical composition.Type: ApplicationFiled: June 22, 2020Publication date: March 4, 2021Inventors: Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
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Publication number: 20200407220Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device including a conductive bonding structure disposed between a substrate and a MEMS substrate. An interconnect structure overlies the substrate. The MEMS substrate overlies the interconnect structure and includes a moveable membrane. A dielectric structure is disposed between the interconnect structure and the MEMS substrate. The conductive bonding structure is sandwiched between the interconnect structure and the MEMS substrate. The conductive bonding structure is spaced laterally between sidewalls of the dielectric structure. The conductive bonding structure, the MEMS substrate, and the interconnect structure at least partially define a cavity. The moveable membrane overlies the cavity and is spaced laterally between sidewalls of the conductive bonding structure.Type: ApplicationFiled: October 15, 2019Publication date: December 31, 2020Inventors: Hung-Hua Lin, Chia-Ming Hung, Xin-Hua Huang, Yuan-Chih Hsieh
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Publication number: 20200062587Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.Type: ApplicationFiled: November 4, 2019Publication date: February 27, 2020Inventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Chia-Ming Hung, Shao-Chi Yu, Hung-Hua Lin, Yuan-Chih Hsieh
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Patent number: 10464808Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.Type: GrantFiled: October 2, 2017Date of Patent: November 5, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Chia-Ming Hung, Shao-Chi Yu, Hung-Hua Lin, Yuan-Chih Hsieh