Patents by Inventor Chia-Ming Liang

Chia-Ming Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11004747
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Patent number: 10996262
    Abstract: A reliability determination method, which is configured to test a batch of semiconductor devices, includes: obtaining a Welbull distribution of lifetime of the batch of semiconductor devices; dividing the Welbull distribution into at least a first section and a second section, wherein the first section and the second section meet a confidence interval; generating a first trend line of the first section and a second trend line of the second section according to the first confidence level, in which the first trend line has a first slope and the second trend line has a second slope; determining the first slope exceeds a second slope; and determining a predicted reliability of the batch of the semiconductor device under a target quality level according to the first section.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 4, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Sheng-Hui Liang, Huang-Lang Pai, Chia-Ming Hsu, Chia-Lin Chen
  • Patent number: 10944152
    Abstract: An antenna structure includes a metal frame. The metal frame includes a first gap, a second gap, a third gap, and a fourth gap to separate a first antenna, a second antenna, a third antenna, and a fourth antenna from the metal frame. The metal frame includes a fifth antenna. The first antenna, the second antenna, the third antenna, and the fourth antenna cooperatively form a first multiple-input multiple-output (MIMO) antenna to provide a 4×4 multiple-input multiple-output function in a second frequency band. The first antenna, the second antenna, the third antenna, and the fifth antenna cooperatively form a second MIMO antenna to provide a 4×4 multiple-input multiple-output function in a third frequency band. The first antenna and the third antenna cooperatively form a third MIMO antenna to provide a 2×2 multiple-input multiple-output function in a first frequency band.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 9, 2021
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Jia-Hung Hsiao, Shu-Wei Jhang, Wen-Yuan Chen, Chang-Hsin Ou, Ming-Yu Chou, Chia-Ming Liang, Kuo-Lun Huang
  • Patent number: 10873123
    Abstract: An antenna structure utilizing as radiating elements only the metal frame of an electronic device includes a metal frame, a feeding portion, and a ground point. The metal frame defines a first gap and a second gap. The metal frame forms a radiating portion, a first coupling portion, and a second coupling portion through the first gap and the second gap. When the feed supplies current, the current flows through the radiating portion and, being coupled to the first coupling portion and second coupling portion through the first and second gaps, first, second, and third operating modes at different frequencies can be invoked to generate wireless signals in first, second, and third LTE-A frequency bands.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 22, 2020
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Chia-Ming Liang, Jin-Bo Chen
  • Publication number: 20200345169
    Abstract: The disclosure relates to an extraction device for extracting soluble favors from raw materials that are distributed within liquid. The extraction device includes a first container, a second container, a valve, and an air suction device. The second container is configured for storing the mixture of the raw materials and the liquid. The valve is connected to the second container and the first container. The air suction device is connected to the first container and configured to decrease the internal pressure of the first container to a predetermined value. When the internal pressure of the first container reaches the predetermined value, the valve is activated to connect the first container to the second container. The disclosure also relates to an extracting method for using the extraction device.
    Type: Application
    Filed: December 11, 2019
    Publication date: November 5, 2020
    Inventors: PEI-LING LAI, CHAO HSUAN CHIU, YING LUN HSU, YU-FANG CHEN, CHIA MING LIANG, YU-KAI SU
  • Publication number: 20200321238
    Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Meng-Fang Hsu, Kong-Pin Chang, Chia Ming Liang
  • Publication number: 20200273754
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Patent number: 10692769
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Patent number: 10692750
    Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Meng-Fang Hsu, Kong-Pin Chang, Chia Ming Liang
  • Patent number: 10651090
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Patent number: 10594505
    Abstract: A server system may include a plurality of internal hubs communicatively coupled to a plurality of server nodes. The plurality of internal hubs may communicate with an external hub to transmit broadcast traffic to reach a designated server node. A hub controller, a routing device coupled to the plurality of internal hubs, may select an internal hub from among a plurality of internal hubs based on a link status and a set of hub selection rules. Based on a status of active link and a relative priority of internal hubs, an internal hub is selected as a transmission channel to receive broadcast traffic from the external hub and direct the broadcast traffic to a corresponding server node.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: March 17, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Wei-Yi Chu, Chia-Feng Cheng, Chia-Ming Liang, Meng-Huan Lu
  • Publication number: 20200076059
    Abstract: An antenna structure includes a metal frame. The metal frame includes a first gap, a second gap, a third gap, and a fourth gap to separate a first antenna, a second antenna, a third antenna, and a fourth antenna from the metal frame. The metal frame includes a fifth antenna. The first antenna, the second antenna, the third antenna, and the fourth antenna cooperatively form a first multiple-input multiple-output (MIMO) antenna to provide a 4×4 multiple-input multiple-output function in a second frequency band. The first antenna, the second antenna, the third antenna, and the fifth antenna cooperatively form a second MIMO antenna to provide a 4×4 multiple-input multiple-output function in a third frequency band. The first antenna and the third antenna cooperatively form a third MIMO antenna to provide a 2×2 multiple-input multiple-output function in a first frequency band.
    Type: Application
    Filed: August 20, 2019
    Publication date: March 5, 2020
    Inventors: JIA-HUNG HSIAO, SHU-WEI JHANG, WEN-YUAN CHEN, CHANG-HSIN OU, MING-YU CHOU, CHIA-MING LIANG, KUO-LUN HUANG
  • Publication number: 20200036085
    Abstract: An antenna structure utilizing as radiating elements only the metal frame of an electronic device includes a metal frame, a feeding portion, and a ground point. The metal frame defines a first gap and a second gap. The metal frame forms a radiating portion, a first coupling portion, and a second coupling portion through the first gap and the second gap. When the feed supplies current, the current flows through the radiating portion and, being coupled to the first coupling portion and second coupling portion through the first and second gaps, first, second, and third operating modes at different frequencies can be invoked to generate wireless signals in first, second, and third LTE-A frequency bands.
    Type: Application
    Filed: July 26, 2019
    Publication date: January 30, 2020
    Inventors: CHIA-MING LIANG, JIN-BO CHEN
  • Patent number: 10529862
    Abstract: A semiconductor device includes a substrate, an epitaxial channel structure and a gate structure. The epitaxial channel structure is located above the substrate. The epitaxial channel structure has a bottom and a top. The bottom is between the substrate and the top, and the bottom has a width less than that of the top.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming Liang, Huai-Hsien Chiu, Yi-Shien Mor
  • Publication number: 20190189614
    Abstract: A method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 20, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Juei LEE, Chia-Ming LIANG, Chi-Hsin CHANG, Jin-Aun NG, Yi-Shien MOR, Huai-Hsien CHIU
  • Publication number: 20190067112
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Application
    Filed: October 31, 2017
    Publication date: February 28, 2019
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Patent number: 10211536
    Abstract: An antenna structure includes a housing, a first connecting portion, a matching unit, a second connecting portion, and a first switching circuit. The housing defines a slot, a first gap, and a second gap. The housing is divided into a first portion and a second portion by the slot, the first gap, and the second gap. The second portion is grounded. One end of the first connecting portion electrically connected to the first portion and another end of the first connecting portion electrically connected to a feed point through the matching unit. The first portion is divided into a first radiating portion and a second radiating portion by the first connecting portion. One end of the second connecting portion is electrically connected to the first radiating portion and another end of the second connecting portion is grounded through the first switching circuit.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: February 19, 2019
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Chia-Ming Liang, Sheng-Chieh Liang, Ming-Yu Chou, Chang-Hsin Ou, Cheng-I Chang
  • Patent number: 10204905
    Abstract: A semiconductor structure includes a substrate, a first gate structure, and a second gate structure. The substrate has a plurality of first fins and a plurality of second fins, wherein a first pitch between two adjacent first fins is greater than a second pitch between two adjacent second fins. The first gate structure crosses over the first fins. The second gate structure crosses over the second fins, wherein the second gate structure includes an upper portion having two first sidewalls substantially parallel to each other and a lower portion tapers toward the substrate.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Juei Lee, Chia-Ming Liang, Chi-Hsin Chang, Jin-Aun Ng, Yi-Shien Mor, Huai-Hsien Chiu
  • Publication number: 20180308842
    Abstract: A semiconductor structure includes a substrate, a first gate structure, and a second gate structure. The substrate has a plurality of first fins and a plurality of second fins, wherein a first pitch between two adjacent first fins is greater than a second pitch between two adjacent second fins. The first gate structure crosses over the first fins. The second gate structure crosses over the second fins, wherein the second gate structure includes an upper portion having two first sidewalls substantially parallel to each other and a lower portion tapers toward the substrate.
    Type: Application
    Filed: June 23, 2017
    Publication date: October 25, 2018
    Inventors: Yi-Juei LEE, Chia-Ming LIANG, Chi-Hsin CHANG, Jin-Aun NG, Yi-Shien MOR, Huai-Hsien CHIU
  • Publication number: 20180269099
    Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.
    Type: Application
    Filed: May 14, 2018
    Publication date: September 20, 2018
    Inventors: Harry-Hak-Lay Chuang, Bao-Ru Young, Wei Cheng Wu, Meng-Fang Hsu, Kong-Pin Chang, Chia Ming Liang