Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.

Abstract: A semiconductor device includes a substrate, an interlayer dielectric layer, spacer structures, a gate insulating layer, a first work function metal layer and a metal gate. The interlayer dielectric layer is disposed above the substrate. The spacer structures are located in a trench of the interlayer dielectric. The gate insulating layer is disposed between inner sidewalls of the spacer structures. The gate insulating layer includes a first region doped with dipole dopant and second regions without the dipole dopant. The first region is connected with the second regions. The first region is horizontally located between the first work function metal layer and the spacer structures. The metal gate is disposed above the first work function metal layer. The metal gate is disposed between and in contact with the second regions.

Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Abstract: An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.

Abstract: The disclosure relates to an extraction device for extracting soluble favors from raw materials that are distributed within liquid. The extraction device includes a first container, a second container, a valve, and an air suction device. The second container is configured for storing the mixture of the raw materials and the liquid. The valve is connected to the second container and the first container. The air suction device is connected to the first container and configured to decrease the internal pressure of the first container to a predetermined value. When the internal pressure of the first container reaches the predetermined value, the valve is activated to connect the first container to the second container. The disclosure also relates to an extracting method for using the extraction device.

Abstract: A measurement device includes a base, a platform, a temperature sensor, and a weighing component. The platform is movably disposed on the base. The temperature sensor is disposed on the base or the platform. The weighing component is accommodated in the base. The platform has a weight-measuring area and a temperature-measuring area which is located within the weight-measuring area and corresponding to the temperature sensor.

Abstract: An antenna system for improved satellite communication with a ground-based terminal device includes a first antenna, a feeding point, and a phase modulation unit. The first antenna is on a surface of a back cover of the terminal device, and the first antenna comprises a plurality of radiation units in an array. The feeding point feeds power and signals to the first antenna. The phase modulation unit can adjust the transmission phase of the different radiation units within the first antenna. The present disclosure also provides a wireless terminal.

Abstract: A field-replaceable unit (FRU) identification circuit includes a reference voltage source, a reference resistor, a plurality of comparators, and a plurality of comparator input voltage sources. The reference voltage source provides a reference voltage. A first end of the reference resistor is electrically connected to the reference voltage source. Each comparator has two inputs and an output. A first input of each comparator is electrically connected to a second end of the reference resistor. The comparator input voltage sources each provide a comparator input voltage to the second input of one of the comparators. When an FRU is electrically connected to a circuit board where the FRU identification circuit is located, the outputs of the comparators are set to a distinct combination of logical values that uniquely identifies the FRU.

Abstract: The measurement method includes operations of applying a first gate bias voltage to a gate terminal of a first transistor that is included in a radio frequency (RF) power amplifier during a direct current (DC) measurement period, wherein the first transistor operates in a linear operation mode during the DC measurement period; measuring a first drain-source voltage of the first transistor and a current flowing through the first transistor via a connection node during the DC measurement period; applying a second gate bias voltage and a drain bias voltage to a gate terminal and a drain terminal of a second transistor that is electrically connected to the first transistor via the connection node; and measuring a DC value of the second transistor via the connection node during the DC measurement period.

Abstract: The measurement method includes operations of applying a first gate bias voltage to a gate terminal of a first transistor that is included in a radio frequency (RF) power amplifier during a direct current (DC) measurement period, wherein the first transistor operates in a linear operation mode during the DC measurement period; measuring a first drain-source voltage of the first transistor and a current flowing through the first transistor via a connection node during the DC measurement period; applying a second gate bias voltage and a drain bias voltage to a gate terminal and a drain terminal of a second transistor that is electrically connected to the first transistor via the connection node; and measuring a DC value of the second transistor via the connection node during the DC measurement period.

Abstract: An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.

Abstract: A method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.

Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.

Abstract: An antenna structure includes a metal frame. The metal frame includes a first gap, a second gap, a third gap, and a fourth gap to separate a first antenna, a second antenna, a third antenna, and a fourth antenna from the metal frame. The metal frame includes a fifth antenna. The first antenna, the second antenna, the third antenna, and the fourth antenna cooperatively form a first multiple-input multiple-output (MIMO) antenna to provide a 4×4 multiple-input multiple-output function in a second frequency band. The first antenna, the second antenna, the third antenna, and the fifth antenna cooperatively form a second MIMO antenna to provide a 4×4 multiple-input multiple-output function in a third frequency band. The first antenna and the third antenna cooperatively form a third MIMO antenna to provide a 2×2 multiple-input multiple-output function in a first frequency band.

Abstract: An antenna structure utilizing as radiating elements only the metal frame of an electronic device includes a metal frame, a feeding portion, and a ground point. The metal frame defines a first gap and a second gap. The metal frame forms a radiating portion, a first coupling portion, and a second coupling portion through the first gap and the second gap. When the feed supplies current, the current flows through the radiating portion and, being coupled to the first coupling portion and second coupling portion through the first and second gaps, first, second, and third operating modes at different frequencies can be invoked to generate wireless signals in first, second, and third LTE-A frequency bands.

Abstract: The disclosure relates to an extraction device for extracting soluble favors from raw materials that are distributed within liquid. The extraction device includes a first container, a second container, a valve, and an air suction device. The second container is configured for storing the mixture of the raw materials and the liquid. The valve is connected to the second container and the first container. The air suction device is connected to the first container and configured to decrease the internal pressure of the first container to a predetermined value. When the internal pressure of the first container reaches the predetermined value, the valve is activated to connect the first container to the second container. The disclosure also relates to an extracting method for using the extraction device.

Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.