Abstract: Provided are structures and methods for forming structures with surfaces having a W-shaped profile. An exemplary method includes differentially etching a gate material to a recessed surface including a first and second horn and a valley located therebetween including first and second sections and a middle section therebetween; depositing an etch-retarding layer over the recessed surface including first and second edge regions and a central region therebetween, wherein the first edge region is located over the first horn and the first section, the second edge region is located over the second horn and the second section, the central region is located over the middle region, and the central region is thicker than the first edge region and the second edge region; and performing an etch process to recess the horns to establish the gate material with a W-shaped profile.

Abstract: The present invention provides an image sensing device and an image sensing method. The image sensing device comprises an image sensing array and an image processing circuit. The image sensing array obtains a first frame for a test object, and the first frame comprises a plurality of first pixel values. The image processing circuit analyzes the first frame, and generate an overexposure area for the first pixel values greater than a first threshold in the first frame. Then, the image sensor array obtains a second frame for the overexposure area, and the second frame comprises a plurality of second pixel values. The image processing circuit performs a detection processing on all the first pixel values in the first frame, which retains the first pixel values outside of the overexposure area in the first frame, and replaces the first pixel values in the overexposure area with the second pixel values.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: The present invention provides an image sensing device and an image sensing method. The image sensing device comprises an image sensing array and an image processing circuit. The image sensing array obtains a first frame for a test object, and the first frame comprises a plurality of first pixel values. The image processing circuit analyzes the first frame, and generate an overexposure area for the first pixel values greater than a first threshold in the first frame. Then, the image sensor array obtains a second frame for the overexposure area, and the second frame comprises a plurality of second pixel values. The image processing circuit performs a detection processing on all the first pixel values in the first frame, which retains the first pixel values outside of the overexposure area in the first frame, and replaces the first pixel values in the overexposure area with the second pixel values.

Abstract: The present invention relates to a nicotinohydrazide derivative, a stereoisomer thereof or a pharmaceutically acceptable salt thereof having a structure of formula (I): wherein each of X, Y and Z is one of N and CH, at least one of X, Y and Z is CH, at least one of X, Y and Z is N, and R is one of OH and NH2.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: The present invention discloses a nanoparticle control and detection system and operating method thereof. The present invention controls and detects the nanoparticles in the same device. The device comprises a first transparent electrode, a photoconductive layer, a spacer which is deposed on the edge of the photoconductive layer and a second transparent electrode. The aforementioned device controls and detects the nanoparticles by applying AC/DC bias and AC/DC light source to the transparent electrode.

Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.

Abstract: The present disclosure provides an electronic package. The electronic package includes a substrate, an electronic component, a plurality of conductive elements, a metal sheet and a molding layer. The electronic component is disposed on the substrate and electrically connected to the substrate. The conductive elements are disposed on the substrate and electrically connected with the grounding circuit on the substrate. The metal sheet is disposed above the electronic component and is in electrical contact with the conductive elements. The molding layer is formed between the substrate and the metal sheet to enclose the electronic component and the conductive elements. The present disclosure further provides a method of manufacturing the above electronic package.

Abstract: The wafer thinning method of the present disclosure includes: providing a wafer having a front surface and a back surface opposite to the front surface; grinding the back surface of the wafer with a grinding bit to thin the wafer to a predetermined thickness; dicing the wafer with a dicing blade; ablating the wafer by performing a chemical solution or plasma process on the back surface of the wafer to thin the wafer; and separating the wafer into a plurality of dies.

Abstract: A method is provided to fabricate a high-power module. A non-touching needle is used to paste a slurry on a heat-dissipation substrate. The slurry comprises nano-silver particles and micron silver particles. The ratio of the two silver particles is 9:1˜1:1. The slurry is pasted on the substrate to be heated up to a temperature kept holding. An integrated chip (IC) is put above the substrate to form a combined piece. A hot presser processes thermocompression to the combined piece to form a thermal-interface-material (TIM) layer with the IC and the substrate. After heat treatment, the TIM contains more than 99 percent of pure silver with only a small amount of organic matter. No volatile organic compounds would be generated after a long term of use. No intermetallic compounds would be generated while the stability under high temperature is obtained. Consequently, embrittlement owing to procedure temperature is dismissed.

Abstract: The present disclosure provides an electronic package. The electronic package includes a substrate, an electronic component, a plurality of conductive elements, a metal sheet and a molding layer. The electronic component is disposed on the substrate and electrically connected to the substrate. The conductive elements are disposed on the substrate and electrically connected with the grounding circuit on the substrate. The metal sheet is disposed above the electronic component and is in electrical contact with the conductive elements. The molding layer is formed between the substrate and the metal sheet to enclose the electronic component and the conductive elements. The present disclosure further provides a method of manufacturing the above electronic package.

Abstract: The method of manufacturing a semiconductor package of the present disclosure includes: providing a redistribution layer having opposing first surface and second surface; disposing a die on the first surface of the redistribution layer and electrically connecting the die to the redistribution layer; forming a mask on the second surface of the redistribution layer; performing a chemical or plasma etching process on the second surface of the redistribution layer to expose the conductive traces in the redistribution layer; removing the mask; and forming a plurality of conductive bumps on the second surface of the redistribution layer and electrically connecting the conductive bumps to the exposed conductive traces in the redistribution layer.

Abstract: The present disclosure provides a semiconductor package. The semiconductor package includes a redistribution layer, a die, a heat spreader, a thermal interface material and a molding layer. The die is disposed on the redistribution layer. The heat spreader is disposed on the die. The thermal interface material is applied between the heat spreader and the die. The molding layer is formed on the redistribution layer to enclose the die. The present disclosure further provides a method of manufacturing the above semiconductor package.

Abstract: The method of manufacturing a semiconductor package of the present disclosure includes: providing a redistribution layer having opposing first surface and second surface; disposing a die on the first surface of the redistribution layer and electrically connecting the die to the redistribution layer; forming a mask on the second surface of the redistribution layer; performing a chemical or plasma etching process on the second surface of the redistribution layer to expose the conductive traces in the redistribution layer; removing the mask; and forming a plurality of conductive bumps on the second surface of the redistribution layer and electrically connecting the conductive bumps to the exposed conductive traces in the redistribution layer.

Abstract: A high temperature reaction system includes a reaction tube including a heating space, a discharge unit, a cooling unit, a feeding unit and an observation and analysis unit. The discharge unit is disposed opposite to an inlet of the heating space and has a discharge space communicating the heating space, and an observation window and a discharge opening which communicate the discharge space. The cooling unit has a cooling space communicating the discharge opening. The feeding unit includes a carrier holding a sample, and a moving module for moving the carrier and the sample. The observation and analysis unit includes an image capture module and an analysis module for analyzing gas released by the sample.

Abstract: A high temperature reaction system includes a reaction tube including a heating space, a discharge unit, a cooling unit, a feeding unit and an observation and analysis unit. The discharge unit is disposed opposite to an inlet of the heating space and has a discharge space communicating the heating space, and an observation window and a discharge opening which communicate the discharge space. The cooling unit has a cooling space communicating the discharge opening. The feeding unit includes a carrier holding a sample, and a moving module for moving the carrier and the sample. The observation and analysis unit includes an image capture module and an analysis module for analyzing gas released by the sample.

Abstract: The present invention discloses a nanoparticle control and detection system and operating method thereof. The present invention controls and detects the nanoparticles in the same device. The device comprises a first transparent electrode, a photoconductive layer, a spacer which is deposed on the edge of the photoconductive layer and a second transparent electrode. The aforementioned device controls and detects the nanoparticles by applying AC/DC bias and AC/DC light source to the transparent electrode.