Abstract: A semiconductor device for testing a semiconductor process applied to manufacturing the semiconductor device is disclosed. The semiconductor device includes at least a testing group. The testing group includes a first testing block and a second testing block. The first testing block includes: a first input node; a first output node; a plurality of first selecting nodes; a first reference device, coupled to the first input node and the first output node; and a first target device, coupled to the first selecting nodes and the first output node. The second testing block includes: a second input node; a second output node; a plurality of second selecting nodes; a second reference device, coupled to the second input node and the second output node; and a second target device, coupled to the second selecting nodes and the second output node.

Abstract: A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP component are classified in response to connection of the input pins. Partial circuits of the IP component are extracted for simulation. Three corners of IP library are generated. Therefore, input capacitance of the IP component is simulated.

Abstract: In order to reduce the leakage current and increase the ESD protection performance, several MOS capacitors are serially connected. The E field between the gate and the source/drain of the MOS transistor is lowered and so is the gate leakage current. Besides, because the ESD voltage is distributed on the gates of the MOS capacitors, the MOS capacitors have good ESD protection performance.

Abstract: A semiconductor device for testing a semiconductor process applied to manufacturing the semiconductor device is disclosed. The semiconductor device includes at least a testing group. The testing group includes a first testing block and a second testing. The first testing block includes: a first input node; a first output node; a plurality of first selecting nodes; a first reference device, coupled to the first input node and the first output node; and a first target device, coupled to the first selecting nodes and the first output node. The second testing block includes: a second input node; a second output node; a plurality of second selecting nodes; a second reference device, coupled to the second input node and the second output node; and a second target device, coupled to the second selecting nodes and the second output node.

Abstract: A methodology for characterization of an IP (Intellectual Property) component is provided. Digital pins are recognized by skipping analog pins and special IO pins. First two layers of the IP component are classified in response to connection of the input pins. Partial circuits of the IP component are extracted for simulation. Three corners of IP library are generated. Therefore, input capacitance of the IP component is simulated.

Abstract: An integrated circuit chip with a high area utilization rate includes: a plurality of logic circuits in a logic area; a first input and output circuit near a first side of the logic area for exchanging signals with the logic circuit; a second input and output circuit near a second side of the logic area for exchanging signals with the logic circuit; a plurality of first probe pads coupled to the first and the second input and output circuits for inputting or outputting signals to the first and the second input and output circuits; a corner cell comprising a plurality of wires coupled to the first and the second input and output circuits for exchanging signals between the first and the second input and output circuits; and a first process monitor circuit formed in the corner cell for monitoring a semiconductor process of the integrated circuit chip.

Abstract: A method of analyzing a correlation among four variables in a two dimensions configuration and a computer accessible medium for storing a program thereof are provided. The method comprises providing a plurality of data comprising a first variable, a second variable, a third variable and a fourth variable. The first to the fourth variables have correlations. Then the data are marked in the two-dimension configuration according to the first and the second variables. The group correlation is marked according to the third variable. The character of the fourth variable is shown by a predetermined method in the two-dimension configuration according to the fourth variable.

Abstract: An integrated circuit chip with a high area utilization rate includes: a plurality of logic circuits in a logic area; a first input and output circuit near a first side of the logic area for exchanging signals with the logic circuit; a second input and output circuit near a second side of the logic area for exchanging signals with the logic circuit; a plurality of first probe pads coupled to the first and the second input and output circuits for inputting or outputting signals to the first and the second input and output circuits; a corner cell comprising a plurality of wires coupled to the first and the second input and output circuits for exchanging signals between the first and the second input and output circuits; and a first process monitor circuit formed in the corner cell for monitoring a semiconductor process of the integrated circuit chip.