Patents by Inventor CHIA-NAN YUAN
CHIA-NAN YUAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240107780Abstract: A system on chip (SoC) die package is attached to a redistribution structure of a semiconductor device package such that a top surface of the SoC die package is above a top surface of an adjacent memory die package. This may be achieved through the use of various attachment structures that increase the height of the SoC die package. After encapsulating the memory die package and the SoC die package in an encapsulation layer, the encapsulation layer is grinded down. The top surface of the SoC die package being above the top surface of the adjacent memory die package results in the top surface of the SoC die package being exposed through the encapsulation layer after the grinding operation. This enables heat to be dissipated through the top surface of the SoC die package.Type: ApplicationFiled: January 5, 2023Publication date: March 28, 2024Inventors: Chih-Wei WU, Ying-Ching SHIH, Wen-Chih CHIOU, An-Jhih SU, Chia-Nan YUAN
-
Patent number: 11935836Abstract: A semiconductor device includes a bridge and a first integrated circuit. The bridge is free of active devices and includes a first conductive connector. The first integrated circuit includes a substrate and a second conductive connector disposed in a first dielectric layer over the substrate. The second conductive connector is directly bonded to the first conductive connector. The second conductive connector includes conductive pads and first conductive vias and a second conductive via between the conductive pads. The second conductive via is not overlapped with the first conductive vias while the first conductive vias are overlapped with one another. A vertical distance between the second conductive via and the first conductive connector is larger than a vertical distance between each of the first conductive vias and the first conductive connector, and a sidewall of the first dielectric layer is substantially flush with a sidewall of the substrate.Type: GrantFiled: August 9, 2022Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Lin, An-Jhih Su, Der-Chyang Yeh, Shih-Guo Shen, Chia-Nan Yuan, Ming-Shih Yeh
-
Publication number: 20230036283Abstract: A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, and a second encapsulant. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die.Type: ApplicationFiled: October 5, 2022Publication date: February 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Lin, Chih-Wei Wu, Chia-Nan Yuan, Ying-Ching Shih, An-Jhih Su, Szu-Wei Lu, Ming-Shih Yeh, Der-Chyang Yeh
-
Publication number: 20220384350Abstract: A semiconductor device includes a bridge and a first integrated circuit. The bridge is free of active devices and includes a first conductive connector. The first integrated circuit includes a substrate and a second conductive connector disposed in a first dielectric layer over the substrate. The second conductive connector is directly bonded to the first conductive connector. The second conductive connector includes conductive pads and first conductive vias and a second conductive via between the conductive pads. The second conductive via is not overlapped with the first conductive vias while the first conductive vias are overlapped with one another. A vertical distance between the second conductive via and the first conductive connector is larger than a vertical distance between each of the first conductive vias and the first conductive connector, and a sidewall of the first dielectric layer is substantially flush with a sidewall of the substrate.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Lin, An-Jhih Su, Der-Chyang Yeh, Shih-Guo Shen, Chia-Nan Yuan, Ming-Shih Yeh
-
Patent number: 11482497Abstract: A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, a second encapsulant and a first RDL structure. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die. The first RDL structure is disposed on the bridge die and the second encapsulant.Type: GrantFiled: January 14, 2021Date of Patent: October 25, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Lin, Chih-Wei Wu, Chia-Nan Yuan, Ying-Ching Shih, An-Jhih Su, Szu-Wei Lu, Ming-Shih Yeh, Der-Chyang Yeh
-
Patent number: 11450612Abstract: A semiconductor device includes a bridge and a plurality of dies. The bridge is free of active devices and includes a substrate, an interconnect structure, a redistribution layer structure and a plurality of conductive connectors. The interconnect structure includes at least one dielectric layer and a plurality of first conductive features in the at least one dielectric layer. The redistribution layer structure includes at least one polymer layer and a plurality of second conductive features in the at least one polymer layer, wherein a sidewall of the interconnect structure is substantially flush with a sidewall of the redistribution layer structure. The conductive connectors are electrically connected to one another by the redistribution layer structure and the interconnect structure. The bridge electrically connects the plurality of dies.Type: GrantFiled: July 9, 2020Date of Patent: September 20, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hung Lin, An-Jhih Su, Der-Chyang Yeh, Shih-Guo Shen, Chia-Nan Yuan, Ming-Shih Yeh
-
Publication number: 20220223534Abstract: A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, a second encapsulant and a first RDL structure. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die. The first RDL structure is disposed on the bridge die and the second encapsulant.Type: ApplicationFiled: January 14, 2021Publication date: July 14, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Lin, Chih-Wei Wu, Chia-Nan Yuan, Ying-Ching Shih, An-Jhih Su, Szu-Wei Lu, Ming-Shih Yeh, Der-Chyang Yeh
-
Publication number: 20220013461Abstract: A semiconductor device includes a bridge and a plurality of dies. The bridge is free of active devices and includes a substrate, an interconnect structure, a redistribution layer structure and a plurality of conductive connectors. The interconnect structure includes at least one dielectric layer and a plurality of first conductive features in the at least one dielectric layer. The redistribution layer structure includes at least one polymer layer and a plurality of second conductive features in the at least one polymer layer, wherein a sidewall of the interconnect structure is substantially flush with a sidewall of the redistribution layer structure. The conductive connectors are electrically connected to one another by the redistribution layer structure and the interconnect structure. The bridge electrically connects the plurality of dies.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hung Lin, An-Jhih Su, Der-Chyang Yeh, Shih-Guo Shen, Chia-Nan Yuan, Ming-Shih Yeh
-
Publication number: 20210281037Abstract: In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.Type: ApplicationFiled: April 26, 2021Publication date: September 9, 2021Inventors: Chen-Hua Yu, An-Jhih Su, Chia-Nan Yuan, Shih-Guo Shen, Der-Chyang Yeh, Yu-Hung Lin, Ming Shih Yeh
-
Patent number: 10992100Abstract: In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.Type: GrantFiled: December 3, 2018Date of Patent: April 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, An-Jhih Su, Chia-Nan Yuan, Shih-Guo Shen, Der-Chyang Yeh, Yu-Hung Lin, Ming Shih Yeh
-
Publication number: 20200014169Abstract: In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.Type: ApplicationFiled: December 3, 2018Publication date: January 9, 2020Inventors: Chen-Hua Yu, An-Jhih Su, Chia-Nan Yuan, Shih-Guo Shen, Der-Chyang Yeh, Yu-Hung Lin, Ming Shih Yeh
-
Publication number: 20120047813Abstract: A cutting fluid for processing is revealed. The cutting fluid for wafer processing includes a cutting solvent, a plurality of cutting particles and a surfactant that induces hydrogen bonding. The surfactant that induces hydrogen bonding contains amine functional groups or acid functional groups. The hydrogen-bonding-inducing surfactant is used to form intermolecular hydrogen bonding so as to improve the suspension stability of the cutting particles in the cutting fluid. The surfactant that induces hydrogen bonding will not change the properties of the cutting fluid so that the following processes will not be affected.Type: ApplicationFiled: November 17, 2010Publication date: March 1, 2012Applicant: NATIONAL CENTRAL UNIVERSITYInventors: HENG-KWONG TSAO, CHIA-NAN YUAN