Abstract: A walking aid device includes a support body inclusive of a plurality of support elements extending toward the ground. Each support element is coupled to a caster and a brake unit. Each brake unit has a clutching surface. The clutching surface controllably clutches a wheel of the caster or the ground to thereby generate friction for stopping the walking aid device.

Abstract: A walking aid device includes a support body inclusive of a plurality of support elements extending toward the ground. Each support element is coupled to a caster and a brake unit. Each brake unit has a clutching surface. The clutching surface controllably clutches a wheel of the caster or the ground to thereby generate friction for stopping the walking aid device.

Abstract: A data write in control circuit for magnetic random access memory is configured with a first transistor, a second transistor connected to the first transistor, a transmission gate connected to the first transistor, a comparator having two input terminal connected to the first transistor, a storage capacitor having one end connected to the first transistor and the other end connected to a power source or a ground, and a logic circuit having one end connected to the output terminal of the comparator and the other end receiving data to be written in.

Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node. The source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes. The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.

Abstract: A method of resolving display delay includes dividing a period of turning on scan lines of an image into at least two sections. At least one section of the period is for charging pixels while pixels are discharged during the other sections of the period for enabling the charging of scan lines (i.e., enabling pixel displaying). The discharging of scan lines (i.e., erasing pixel displaying) is performed a designated number of scan lines apart so as to achieve the purpose of preventing the liquid crystal display from generating display delay and exhibiting an image-sticking phenomena.

Abstract: A memory structure and data writing method thereof includes a power supply circuit and a bridge circuit. The bridge circuit is driven by the power supply circuit, and operate in a plurality of conduction modes. The memory structure only requires one set of power supply circuit and does not need to know the resistance of the bit line in advance, also the signal error is hardly occurred when the memory structure is switching between positive and negative.

Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell with changeable resistance and a plurality of reference cells. The first current mirror circuit, coupled to the output terminal of the memory cell, generates a second memory cell current at a first node according to a first memory cell current through the memory cell. The second current mirror circuit, coupled to the output terminal of the reference cells, generates a plurality of second reference currents at a plurality of second nodes according to a plurality of first reference currents through the reference cells. The load circuit, coupled to the first node, the second nodes, and a ground, provides equal loads for the second memory cell current and the second reference currents to respectively generate a memory cell voltage at the first node and a plurality of reference voltages at the second nodes.

Abstract: A data write in control circuit for magnetic random access memory is configured with a first transistor, a second transistor connected to the first transistor, a transmission gate connected to the first transistor, a comparator having two input terminal connected to the first transistor, a storage capacitor having one end connected to the first transistor and the other end connected to a power source or a ground, and a logic circuit having one end connected to the output terminal of the comparator and the other end receiving data to be written in.

Abstract: The invention relates to a sense amplifier comprising the following element: a first current mirror unit coupled to a high voltage source, outputting a first current and a second current according to a first reference current, wherein the second current is twice the first current; a second current mirror unit coupled to a high voltage source, outputting a third current according to a second reference current; a first impedor coupled to the second current and a low voltage source; a second impedor coupled to the third current and a low voltage source; a third current mirror coupled to the first, second and third currents, and the first current is regarded as the reference current of the third current mirror unit, thus, the current which flows through the first impedor is the first current, and the current which flows through the second impedor is a fourth current.

Abstract: A memory device is provided. The device comprises a sense amplifier having a cell input terminal and a reference input terminal, a first sub-array coupled to the cell input terminal through a first switch and coupled to the reference input terminal through a second switch, a second sub-array coupled to the cell input terminal through a third switch and coupled to the reference input terminal through a fourth switch, and a reference cell array coupled between the second switch and the fourth switch and coupled to the reference input terminal.

Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell and a plurality of reference cells. The source follower, coupled between a first node and the output terminal of the memory cell, clamps the voltage drop across the memory cell to generate a memory cell current flowing through the first node. The source follower circuit, coupled between a plurality of second nodes and the output terminals of the reference cells, clamps the voltage drops across the reference cells to generate a plurality of reference currents respectively flowing through the second nodes. The current mirror circuit, coupled to the first node and the second nodes, duplicates the memory cell current of the first node to affect the reference currents on the second nodes, thereby generating a memory cell voltage on the first node and a plurality of reference voltages on the second nodes.

Abstract: The invention provides a multi-state sense amplifier, coupled to at least one memory cell with changeable resistance and a plurality of reference cells. The first current mirror circuit, coupled to the output terminal of the memory cell, generates a second memory cell current at a first node according to a first memory cell current through the memory cell. The second current mirror circuit, coupled to the output terminal of the reference cells, generates a plurality of second reference currents at a plurality of second nodes according to a plurality of first reference currents through the reference cells. The load circuit, coupled to the first node, the second nodes, and a ground, provides equal loads for the second memory cell current and the second reference currents to respectively generate a memory cell voltage at the first node and a plurality of reference voltages at the second nodes.

Abstract: Scan driver and driving system with low input voltage and their level shift circuit are disclosed. The scan driver includes a latch unit, a level shift circuit and a buffer. The latch unit generates a first control signal and a second control signal. The level shift circuit is connected to the latch unit to receive the first control signal, the second control signal, a first clock signal and a second clock signal, so as to output a scan signal with high voltage level. The buffer enhances driving ability of the scan signal for driving thin-film transistors (TFTs) of a display panel.

Abstract: The invention relates to a sense amplifier comprising the following element: a first current mirror unit coupled to a high voltage source, outputting a first current and a second current according to a first reference current, wherein the second current is twice the first current; a second current mirror unit coupled to a high voltage source, outputting a third current according to a second reference current; a first impedor coupled to the second current and a low voltage source; a second impedor coupled to the third current and a low voltage source; a third current mirror coupled to the first, second and third currents, and the first current is regarded as the reference current of the third current mirror unit, thus, the current which flows through the first impedor is the first current, and the current which flows through the second impedor is a fourth current.

Abstract: A memory structure and data writing method thereof includes a power supply circuit and a bridge circuit. The bridge circuit is driven by the power supply circuit, and operate in a plurality of conduction modes. The memory structure only requires one set of power supply circuit and does not need to know the resistance of the bit line in advance, also the signal error is hardly occurred when the memory structure is switching between positive and negative.

Abstract: A memory device is provided. The device comprises a sense amplifier having a cell input terminal and a reference input terminal, a first sub-array coupled to the cell input terminal through a first switch and coupled to the reference input terminal through a second switch, a second sub-array coupled to the cell input terminal through a third switch and coupled to the reference input terminal through a fourth switch, and a reference cell array coupled between the second switch and the fourth switch and coupled to the reference input terminal.

Abstract: A thin-film transistor (TFT) is described to have a gate layer, an insulating layer, a semiconductor layer, and a source/drain layer formed on a flexible substrate. The source and the drain layers are separated by a channel with a special shape. This does not only increase the aspect ratio of the channel per unit area, the source and the drain also have multiple directions for transmitting carriers. The carrier mobility of the TFT is thus enhanced with uniform and stable circuit properties.

Abstract: A method of resolving display delay is disclosed. The method of resolving display delay comprises the steps of: dividing a period of turning on scan lines of an image is into at least two sections; and charging at least one section of the period while discharging the other sections of the period for enabling the charging of scan lines (i.e. enabling pixel displaying) and the discharging of scan lines (i.e. erasing pixel displaying) are performed with a designated number of scan lines apart so as to achieve the purpose of preventing the liquid crystal display from generating display delay and image-sticking phenomena.

Abstract: Scan driver and driving system with low input voltage and their level shift circuit are disclosed. The scan driver includes a latch unit, a level shift circuit and a buffer. The latch unit generates a first control signal and a second control signal. The level shift circuit is connected to the latch unit to receive the first control signal, the second control signal, a first clock signal and a second clock signal, so as to output a scan signal with high voltage level. The buffer enhances driving ability of the scan signal for driving thin-film transistors (TFTs) of a display panel.