Patents by Inventor Chia-Pin CHANG

Chia-Pin CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128868
    Abstract: A switching regulator includes: a power stage circuit; a control circuit; and an operation clock signal generator circuit configured to generate plural test clock signals during a clock determination period and generate an operation clock signal during a normal operation period. When the switching regulator operates during the clock determination period in a discontinuous conduction mode, the control circuit alternatingly generates plural PWM signals corresponding to the test clock signals generated by the operation clock signal generator circuit and an output voltage, wherein each PWM signal corresponds to one test clock signal, so that the power stage circuit generates corresponding phase node voltages at a phase node, wherein among the plural test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.
    Type: Application
    Filed: September 21, 2023
    Publication date: April 18, 2024
    Inventors: Chia-Jung Chang, Shao-Ming Chang, Tsan-He Wang, Jiing-Horng Wang, Yu-Pin Tseng
  • Publication number: 20240113203
    Abstract: A method includes providing a fin extending from a substrate, the fin including a plurality of semiconductor channel layers, and where a gate is disposed over the fin. A first spacer layer is deposited over the gate and over the fin in a source/drain region. The first spacer layer has a first etch rate. A second spacer layer is deposited over the first spacer layer. The second spacer layer has a second etch rate less than the first etch rate. The plurality of semiconductor channel layers are removed from the source/drain region to form a trench having a funnel shape. After forming the trench, inner spacers are formed along a sidewall surface of the trench. In various embodiments, lateral sidewall surfaces of each semiconductor channel layer of the plurality of semiconductor channel layers is substantially free of an inner spacer material.
    Type: Application
    Filed: January 25, 2023
    Publication date: April 4, 2024
    Inventors: Che-Lun CHANG, Wei-Yang LEE, Chia-Pin LIN
  • Patent number: 11935781
    Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Lun Chang, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
  • Patent number: 11921101
    Abstract: Disclosed are calibration techniques that can be implemented by a device that conducts biological tests. In certain embodiments, the device for testing a biological specimen includes a receiving mechanism to receive a carrier, a camera module arranged to capture imagery of the carrier, and a processor. Some examples of the processor can detect a calibration mode trigger. In calibration mode, the processor can divide the captured imagery into segments and selectively perform one or more calibration procedures for each segment. Then, the processor records a calibration result for each segment.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: March 5, 2024
    Assignee: Bonraybio Co., Ltd.
    Inventors: Cheng-Teng Hsu, Chih-Pin Chang, Kuang-Li Huang, Yu-Chiao Chi, Chia-Wei Chang, Chiung-Han Wang
  • Patent number: 10990343
    Abstract: A movable display device includes a carrying module, a lifting module, a frame module and a display module. The carrying module includes a carrier unit, a base unit disposed on the carrier unit, and a plurality of positioning units disposed on the carrier unit. The lifting module is disposed on the base unit. The frame module includes a primary frame unit movably connected to the positioning units and a plurality of secondary frame units movably connected to the primary frame unit. The primary frame unit has a connecting portion connected to the lifting module. The secondary frame units are respectively located at two sides of the primary frame unit. The display module includes a primary display unit disposed on the primary frame unit and a plurality of secondary display units respectively disposed on the secondary frame units.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: April 27, 2021
    Assignee: HARVATEK CORPORATION
    Inventors: Yung-Pao Tang, Yen-Chun Wang, Shou-Li Chang, Chia-Pin Chang, Feng-Hui Chuang
  • Publication number: 20200233627
    Abstract: A movable display device includes a carrying module, a lifting module, a frame module and a display module. The carrying module includes a carrier unit, a base unit disposed on the carrier unit, and a plurality of positioning units disposed on the carrier unit. The lifting module is disposed on the base unit. The frame module includes a primary frame unit movably connected to the positioning units and a plurality of secondary frame units movably connected to the primary frame unit. The primary frame unit has a connecting portion connected to the lifting module. The secondary frame units are respectively located at two sides of the primary frame unit. The display module includes a primary display unit disposed on the primary frame unit and a plurality of secondary display units respectively disposed on the secondary frame units.
    Type: Application
    Filed: January 20, 2020
    Publication date: July 23, 2020
    Inventors: Yung-Pao Tang, YEN-CHUN WANG, SHOU-LI CHANG, Chia-Pin CHANG, FENG-HUI CHUANG
  • Patent number: 10084123
    Abstract: An LED package structure without pre-stored power sources includes a substrate unit and a LED chip. The substrate unit includes a carrier substrate, a positive conductive pin, and a negative conductive pin. The positive conductive pin is made of a first predetermined material with positive oxidation-reduction potential. The negative conductive pin is made of a second predetermined material with negative oxidation-reduction potential. The LED chip is disposed on the carrier substrate and electrically connected between the positive conductive pin and the negative conductive pin. Both the positive conductive pin and the negative conductive pin concurrently contact a predetermined liquid for generating oxidation-reduction reaction so as to generate electric powers with a predetermined driving voltage, and the LED chip is driven by the electric powers with the predetermined driving voltage for generating an indicator light source.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: September 25, 2018
    Assignee: HARVATEK CORPORATION
    Inventors: Hsin I Lu, Yu Ping Wang, Chia Pin Chang, Hui Yen Huang
  • Publication number: 20170033270
    Abstract: An LED package structure without pre-stored power sources includes a substrate unit and a LED chip. The substrate unit includes a carrier substrate, a positive conductive pin, and a negative conductive pin. The positive conductive pin is made of a first predetermined material with positive oxidation-reduction potential. The negative conductive pin is made of a second predetermined material with negative oxidation-reduction potential. The LED chip is disposed on the carrier substrate and electrically connected between the positive conductive pin and the negative conductive pin. Both the positive conductive pin and the negative conductive pin concurrently contact a predetermined liquid for generating oxidation-reduction reaction so as to generate electric powers with a predetermined driving voltage, and the LED chip is driven by the electric powers with the predetermined driving voltage for generating an indicator light source.
    Type: Application
    Filed: January 19, 2016
    Publication date: February 2, 2017
    Inventors: Hsin I Lu, Yu Ping Wang, Chia Pin Chang, Hui Yen Huang
  • Patent number: 9224718
    Abstract: A white light-emitting diode (LED) package containing plural blue LED chips is disclosed. The white LED package includes a transparent plate, plural blue LED chips bonded on a front surface of the transparent plate, a front fluorescent glue layer covering the plural blue LED chips, and a rear transparent glue layer covering a rear surface of the transparent plate and located at a position aligned with the front fluorescent glue layer. The edge of the rear transparent glue layer has an inclined lateral surface or a curved inclined lateral surface. Therefore, the light can be extracted from both front and rear surfaces, and the light extraction efficiency of the rear surface of the transparent plate is increased. The rear transparent glue layer can be replaced by a rear fluorescent glue layer to reduce the color temperature difference between the lights extracted from the front surface and the rear surface.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: December 29, 2015
    Assignee: Harvatek Corporation
    Inventors: Tsung-Kan Cheng, Chia-Chin Chen, Chia-Pin Chang
  • Publication number: 20140209934
    Abstract: A white light-emitting diode (LED) package containing plural blue LED chips is disclosed. The white LED package includes a transparent plate, plural blue LED chips bonded on a front surface of the transparent plate, a front fluorescent glue layer covering the plural blue LED chips, and a rear transparent glue layer covering a rear surface of the transparent plate and located at a position aligned with the front fluorescent glue layer. The edge of the rear transparent glue layer has an inclined lateral surface or a curved inclined lateral surface. Therefore, the light can be extracted from both front and rear surfaces, and the light extraction efficiency of the rear surface of the transparent plate is increased. The rear transparent glue layer can be replaced by a rear fluorescent glue layer to reduce the color temperature difference between the lights extracted from the front surface and the rear surface.
    Type: Application
    Filed: November 11, 2013
    Publication date: July 31, 2014
    Applicant: Harvatek Corporation
    Inventors: Tsung-Kan CHENG, Chia-Chin CHEN, Chia-Pin CHANG
  • Publication number: 20120261256
    Abstract: This invention has two synergistic elements for simultaneous use in point-of-care or field analyses of diverse substances important to clinical medicine and other applications. The first element is a sample holder in which are stored the several reagents need for quantification of target molecules. The onboard storage of reagents in a water soluble plastic obviates the need for purchase, storage, measuring and mixing of the required reagents prior to analyses. The second part of the invention is a compact hand-held analyzer made of modern miniature optical components, into which the holder is inserted right after it is loaded with a sample by capillary action. The combination of the holder and analyzer permits analyses that are ten times faster than those done with current analyzers, and equally accurate. Analyses can be performed by diverse people, who require only a few minutes of training in the use of the entire invention.
    Type: Application
    Filed: February 22, 2012
    Publication date: October 18, 2012
    Inventors: Chia-Pin CHANG, David J. Nagel
  • Publication number: 20110316145
    Abstract: A nano/micro-structure and a fabrication method thereof are provided. The method combines electroless plating and metal-assist etching to fabricate nano/micro-structure on a silicon substrate.
    Type: Application
    Filed: February 1, 2011
    Publication date: December 29, 2011
    Applicant: NATIONAL CENTRAL UNIVERSITY
    Inventors: Chia-Wen TSAO, Chia-Pin CHANG, Wen-Yih CHEN, Chih-Cheng CHIEN, Yu-Che CHENG