Patents by Inventor Chia-Pin Cheng
Chia-Pin Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923409Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.Type: GrantFiled: August 5, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
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Publication number: 20230378205Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures. The semiconductor device further includes a gate structure. The gate structure includes a first sidewall and a second sidewall angled with respect to the first sidewall. The gate structure further includes a first surface extending between the first sidewall and the second sidewall, wherein a dimension of the gate structure in a first direction is less than a dimension of each of the plurality of isolation structures in the first direction.Type: ApplicationFiled: July 31, 2023Publication date: November 23, 2023Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
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Publication number: 20230369517Abstract: An image sensor device includes nanostructures for improving light absorption efficiency. The image sensor device includes a substrate, a light absorption region, and a nanostructure array. The light absorption region is over the substrate. The nanostructure array us over the light absorption region. The nanostructure array includes a plurality of nanostructures repeatedly arranged from a top view.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Hsiang TSENG, Chih-Fei LEE, Chia-Pin CHENG, Fu-Cheng CHANG
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Patent number: 11784198Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.Type: GrantFiled: June 2, 2022Date of Patent: October 10, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
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Patent number: 11777040Abstract: A semiconductor device includes a substrate, a photo sensing region, and a plurality of semiconductor plugs. The photo sensing region is in the substrate. The photo sensing region forms a p-n junction with the substrate. The semiconductor plugs extend from above the photo sensing region into the photo sensing region.Type: GrantFiled: November 28, 2022Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
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Publication number: 20230106960Abstract: A semiconductor device includes a substrate, a photo sensing region, and a plurality of semiconductor plugs. The photo sensing region is in the substrate. The photo sensing region forms a p-n junction with the substrate. The semiconductor plugs extend from above the photo sensing region into the photo sensing region.Type: ApplicationFiled: November 28, 2022Publication date: April 6, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Hsiang TSENG, Chih-Fei LEE, Chia-Pin CHENG, Fu-Cheng CHANG
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Patent number: 11515435Abstract: A semiconductor device includes a semiconductor substrate, a photo sensing region, and a plurality of nanostructures. The semiconductor substrate has a first dopant. The photo sensing region is embedded in the semiconductor substrate, has a top surface level with a top surface of the semiconductor substrate, and has a second dopant that is of a different conductivity type than the first dopant. The plurality of nanostructures is on the photo sensing region and is made of a material the same as the photo sensing region.Type: GrantFiled: October 9, 2020Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
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Publication number: 20220293650Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.Type: ApplicationFiled: June 2, 2022Publication date: September 15, 2022Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
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Patent number: 11380721Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.Type: GrantFiled: February 13, 2020Date of Patent: July 5, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
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Publication number: 20210028318Abstract: A semiconductor device includes a semiconductor substrate, a photo sensing region, and a plurality of nanostructures. The semiconductor substrate has a first dopant. The photo sensing region is embedded in the semiconductor substrate, has a top surface level with a top surface of the semiconductor substrate, and has a second dopant that is of a different conductivity type than the first dopant. The plurality of nanostructures is on the photo sensing region and is made of a material the same as the photo sensing region.Type: ApplicationFiled: October 9, 2020Publication date: January 28, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Hsiang TSENG, Chih-Fei LEE, Chia-Pin CHENG, Fu-Cheng CHANG
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Patent number: 10804414Abstract: A method of forming a semiconductor device includes forming a photo sensing region in a semiconductor substrate, wherein the semiconductor substrate is of a first type dopant and the photo sensing region is of a second type dopant that has a different conductivity type than the first type dopant; forming a nanostructure layer in contact with an interface between the photo sensing region and the semiconductor substrate; and etching the nanostructure layer until exposing the photo sensing region to form a plurality of nanostructures.Type: GrantFiled: April 22, 2019Date of Patent: October 13, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
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Publication number: 20200185440Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.Type: ApplicationFiled: February 13, 2020Publication date: June 11, 2020Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
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Patent number: 10566361Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.Type: GrantFiled: May 10, 2017Date of Patent: February 18, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Yu Wei, Fu-Cheng Chang, Hsin-Chi Chen, Ching-Hung Kao, Chia-Pin Cheng, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
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Publication number: 20190252559Abstract: A method of forming a semiconductor device includes forming a photo sensing region in a semiconductor substrate, wherein the semiconductor substrate is of a first type dopant and the photo sensing region is of a second type dopant that has a different conductivity type than the first type dopant; forming a nanostructure layer in contact with an interface between the photo sensing region and the semiconductor substrate; and etching the nanostructure layer until exposing the photo sensing region to form a plurality of nanostructures.Type: ApplicationFiled: April 22, 2019Publication date: August 15, 2019Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
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Patent number: 10269990Abstract: A semiconductor device is provided, which includes a substrate and at least one nanostructure. The substrate has sensing pixels, and each of the sensing pixels has a photo sensing region for absorbing incident light. The nanostructure is directly on the photo sensing region. The nanostructure of each of the sensing pixels has a projected portion on an upper surface of the substrate, and a circle equivalent diameter of the projected portion of the nanostructure of each of the sensing pixels is substantially within a wavelength range of 100 nm to 1900 nm of the incident light configured to enter the substrate through the nanostructure.Type: GrantFiled: March 27, 2017Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
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Patent number: 10170515Abstract: A semiconductor device includes a substrate and a device. The substrate has a first surface and a second surface opposite to each other. The substrate includes a first well region, and the first well region includes a first shallow implantation region adjacent to the first surface and a first deep implantation region adjacent to the second surface, in which a dopant concentration of the first deep implantation region at the second surface is substantially equal to 0. The device is disposed on the first surface of the substrate and adjoins the first shallow implantation region.Type: GrantFiled: April 14, 2017Date of Patent: January 1, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Che-Chun Lu, Ching-Hung Kao, Fu-Cheng Chang, Chia-Pin Cheng, Po-Chun Chiu
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Patent number: 10157950Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. An isolation feature is disposed in the semiconductor substrate to define a pixel region and a periphery region of the semiconductor substrate. A transistor gate is formed on the semiconductor substrate in the pixel region, in which the transistor gate has a first sidewall and a second sidewall opposite to the first sidewall. A photodiode is disposed in the semiconductor substrate and adjacent to the second sidewall of the transistor gate. A patterned spacer layer is formed on the photodiode and on the transistor gate. The patterned spacer layer includes a first sidewall spacer on the first sidewall of the transistor gate, and a protective structure covering the photodiode and a top surface of the transistor gate.Type: GrantFiled: January 10, 2018Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Hung Lee, Chia-Pin Cheng, Fu-Cheng Chang, Volume Chien, Ching-Hung Kao
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Patent number: 10157941Abstract: An image sensor and a fabrication method thereof are provided. In the fabrication method of the image sensor, at first, two isolation features are formed in a substrate to define a pixel region. Then, a floating node and a pinning layer are formed in one of the isolation features, in which a space region is located between the floating node and the pinning layer, and the floating node has a first conductivity type different from a second conductivity type of the pinning layer. Thereafter, a light-sensitive element is formed in the pixel region, and a transfer gate is formed on the pixel region, thereby forming a pixel. Since there is a space region located between the floating node and the pinning layer, a leakage path between the floating node and the pinning layer can be prevented.Type: GrantFiled: November 17, 2016Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Pin Cheng, Fu-Cheng Chang, Ching-Hung Kao, Che-Chun Lu
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Patent number: 10115758Abstract: A semiconductor device and a method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, a semiconductor substrate is provided. Then, a trench is formed in the semiconductor substrate. Thereafter, a dielectric layer is formed to cover the semiconductor substrate, in which the dielectric layer has a trench portion located in the trench of the semiconductor substrate. Then, a reflective material layer is formed on the trench portion of the dielectric layer. Thereafter, the reflective material layer is etched to form an isolation structure, in which the isolation structure includes a top portion located on the semiconductor substrate and a bottom portion located in a trench formed by the trench portion of the dielectric layer.Type: GrantFiled: March 8, 2017Date of Patent: October 30, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kai-Yi Chen, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao, Chia-Pin Cheng
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Publication number: 20180301496Abstract: A semiconductor device includes a substrate and a device. The substrate has a first surface and a second surface opposite to each other. The substrate includes a first well region, and the first well region includes a first shallow implantation region adjacent to the first surface and a first deep implantation region adjacent to the second surface, in which a dopant concentration of the first deep implantation region at the second surface is substantially equal to 0. The device is disposed on the first surface of the substrate and adjoins the first shallow implantation region.Type: ApplicationFiled: April 14, 2017Publication date: October 18, 2018Inventors: Che-Chun Lu, Ching-Hung Kao, Fu-Cheng Chang, Chia-Pin Cheng, Po-Chun Chiu