Patents by Inventor Chia-Pin Cheng

Chia-Pin Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190252559
    Abstract: A method of forming a semiconductor device includes forming a photo sensing region in a semiconductor substrate, wherein the semiconductor substrate is of a first type dopant and the photo sensing region is of a second type dopant that has a different conductivity type than the first type dopant; forming a nanostructure layer in contact with an interface between the photo sensing region and the semiconductor substrate; and etching the nanostructure layer until exposing the photo sensing region to form a plurality of nanostructures.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
  • Patent number: 10269990
    Abstract: A semiconductor device is provided, which includes a substrate and at least one nanostructure. The substrate has sensing pixels, and each of the sensing pixels has a photo sensing region for absorbing incident light. The nanostructure is directly on the photo sensing region. The nanostructure of each of the sensing pixels has a projected portion on an upper surface of the substrate, and a circle equivalent diameter of the projected portion of the nanostructure of each of the sensing pixels is substantially within a wavelength range of 100 nm to 1900 nm of the incident light configured to enter the substrate through the nanostructure.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
  • Patent number: 10170515
    Abstract: A semiconductor device includes a substrate and a device. The substrate has a first surface and a second surface opposite to each other. The substrate includes a first well region, and the first well region includes a first shallow implantation region adjacent to the first surface and a first deep implantation region adjacent to the second surface, in which a dopant concentration of the first deep implantation region at the second surface is substantially equal to 0. The device is disposed on the first surface of the substrate and adjoins the first shallow implantation region.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Chun Lu, Ching-Hung Kao, Fu-Cheng Chang, Chia-Pin Cheng, Po-Chun Chiu
  • Patent number: 10157941
    Abstract: An image sensor and a fabrication method thereof are provided. In the fabrication method of the image sensor, at first, two isolation features are formed in a substrate to define a pixel region. Then, a floating node and a pinning layer are formed in one of the isolation features, in which a space region is located between the floating node and the pinning layer, and the floating node has a first conductivity type different from a second conductivity type of the pinning layer. Thereafter, a light-sensitive element is formed in the pixel region, and a transfer gate is formed on the pixel region, thereby forming a pixel. Since there is a space region located between the floating node and the pinning layer, a leakage path between the floating node and the pinning layer can be prevented.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Pin Cheng, Fu-Cheng Chang, Ching-Hung Kao, Che-Chun Lu
  • Patent number: 10157950
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. An isolation feature is disposed in the semiconductor substrate to define a pixel region and a periphery region of the semiconductor substrate. A transistor gate is formed on the semiconductor substrate in the pixel region, in which the transistor gate has a first sidewall and a second sidewall opposite to the first sidewall. A photodiode is disposed in the semiconductor substrate and adjacent to the second sidewall of the transistor gate. A patterned spacer layer is formed on the photodiode and on the transistor gate. The patterned spacer layer includes a first sidewall spacer on the first sidewall of the transistor gate, and a protective structure covering the photodiode and a top surface of the transistor gate.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hung Lee, Chia-Pin Cheng, Fu-Cheng Chang, Volume Chien, Ching-Hung Kao
  • Patent number: 10115758
    Abstract: A semiconductor device and a method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, a semiconductor substrate is provided. Then, a trench is formed in the semiconductor substrate. Thereafter, a dielectric layer is formed to cover the semiconductor substrate, in which the dielectric layer has a trench portion located in the trench of the semiconductor substrate. Then, a reflective material layer is formed on the trench portion of the dielectric layer. Thereafter, the reflective material layer is etched to form an isolation structure, in which the isolation structure includes a top portion located on the semiconductor substrate and a bottom portion located in a trench formed by the trench portion of the dielectric layer.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Yi Chen, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao, Chia-Pin Cheng
  • Publication number: 20180301496
    Abstract: A semiconductor device includes a substrate and a device. The substrate has a first surface and a second surface opposite to each other. The substrate includes a first well region, and the first well region includes a first shallow implantation region adjacent to the first surface and a first deep implantation region adjacent to the second surface, in which a dopant concentration of the first deep implantation region at the second surface is substantially equal to 0. The device is disposed on the first surface of the substrate and adjoins the first shallow implantation region.
    Type: Application
    Filed: April 14, 2017
    Publication date: October 18, 2018
    Inventors: Che-Chun Lu, Ching-Hung Kao, Fu-Cheng Chang, Chia-Pin Cheng, Po-Chun Chiu
  • Publication number: 20180166592
    Abstract: A semiconductor device is provided, which includes a substrate and at least one nanostructure. The substrate has sensing pixels, and each of the sensing pixels has a photo sensing region for absorbing incident light. The nanostructure is directly on the photo sensing region. The nanostructure of each of the sensing pixels has a projected portion on an upper surface of the substrate, and a circle equivalent diameter of the projected portion of the nanostructure of each of the sensing pixels is substantially within a wavelength range of 100 nm to 1900 nm of the incident light configured to enter the substrate through the nanostructure.
    Type: Application
    Filed: March 27, 2017
    Publication date: June 14, 2018
    Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
  • Publication number: 20180166481
    Abstract: A gate structure includes a gate and a first isolation structure having a top surface and a bottom surface. The gate includes a first sidewall adjacent to the first isolation structure, a second sidewall, a first horizontal surface adjacent to a bottom edge of the first sidewall and a bottom edge of the second sidewall, the first horizontal surface being between the top surface of the first isolation structure and the bottom surface of the first isolation structure. The gate also includes a second horizontal surface adjacent to a top edge of the second sidewall. An effective channel width defined by the gate structure includes a height of the second sidewall and a width of the second horizontal surface.
    Type: Application
    Filed: May 10, 2017
    Publication date: June 14, 2018
    Inventors: Chia-Yu WEI, Fu-Cheng CHANG, Hsin-Chi CHEN, Ching-Hung KAO, Chia-Pin CHENG, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Publication number: 20180166476
    Abstract: A semiconductor device and a method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, a semiconductor substrate is provided. Then, a trench is formed in the semiconductor substrate. Thereafter, a dielectric layer is formed to cover the semiconductor substrate, in which the dielectric layer has a trench portion located in the trench of the semiconductor substrate. Then, a reflective material layer is formed on the trench portion of the dielectric layer. Thereafter, the reflective material layer is etched to form an isolation structure, in which the isolation structure includes a top portion located on the semiconductor substrate and a bottom portion located in a trench formed by the trench portion of the dielectric layer.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 14, 2018
    Inventors: Kai-Yi Chen, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao, Chia-Pin Cheng
  • Publication number: 20180158851
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. An isolation feature is disposed in the semiconductor substrate to define a pixel region and a periphery region of the semiconductor substrate. A transistor gate is formed on the semiconductor substrate in the pixel region, in which the transistor gate has a first sidewall and a second sidewall opposite to the first sidewall. A photodiode is disposed in the semiconductor substrate and adjacent to the second sidewall of the transistor gate. A patterned spacer layer is formed on the photodiode and on the transistor gate. The patterned spacer layer includes a first sidewall spacer on the first sidewall of the transistor gate, and a protective structure covering the photodiode and a top surface of the transistor gate.
    Type: Application
    Filed: January 10, 2018
    Publication date: June 7, 2018
    Inventors: Kuo-Hung Lee, Chia-Pin Cheng, Fu-Cheng Chang, Volume Chien, Ching-Hung Kao
  • Publication number: 20180138218
    Abstract: An image sensor and a fabrication method thereof are provided. In the fabrication method of the image sensor, at first, two isolation features are formed in a substrate to define a pixel region. Then, a floating node and a pinning layer are formed in one of the isolation features, in which a space region is located between the floating node and the pinning layer, and the floating node has a first conductivity type different from a second conductivity type of the pinning layer. Thereafter, a light-sensitive element is formed in the pixel region, and a transfer gate is formed on the pixel region, thereby forming a pixel. Since there is a space region located between the floating node and the pinning layer, a leakage path between the floating node and the pinning layer can be prevented.
    Type: Application
    Filed: November 17, 2016
    Publication date: May 17, 2018
    Inventors: Chia-Pin Cheng, Fu-Cheng Chang, Ching-Hung Kao, Che-Chun Lu
  • Patent number: 9887225
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. An isolation feature is disposed in the semiconductor substrate to define a pixel region and a periphery region of the semiconductor substrate. A transistor gate is formed on the semiconductor substrate in the pixel region, in which the transistor gate has a first sidewall and a second sidewall opposite to the first sidewall. A photodiode is disposed in the semiconductor substrate and adjacent to the second sidewall of the transistor gate. A patterned spacer layer is formed on the photodiode and on the transistor gate. The patterned spacer layer includes a first sidewall spacer on the first sidewall of the transistor gate, and a protective structure covering the photodiode and a top surface of the transistor gate.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: February 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hung Lee, Chia-Pin Cheng, Fu-Cheng Chang, Volume Chien, Ching-Hung Kao
  • Publication number: 20170345852
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. An isolation feature is disposed in the semiconductor substrate to define a pixel region and a periphery region of the semiconductor substrate. A transistor gate is formed on the semiconductor substrate in the pixel region, in which the transistor gate has a first sidewall and a second sidewall opposite to the first sidewall. A photodiode is disposed in the semiconductor substrate and adjacent to the second sidewall of the transistor gate. A patterned spacer layer is formed on the photodiode and on the transistor gate. The patterned spacer layer includes a first sidewall spacer on the first sidewall of the transistor gate, and a protective structure covering the photodiode and a top surface of the transistor gate.
    Type: Application
    Filed: August 4, 2016
    Publication date: November 30, 2017
    Inventors: Kuo-Hung Lee, Chia-Pin Cheng, Fu-Cheng Chang, Volume Chien, Ching-Hung Kao
  • Patent number: 9171759
    Abstract: A semiconductor wafer having a plurality of chip die areas arranged on a wafer in an array, each chip die area including a seal ring area with one or more first sets of polygonal structures. The wafer further comprises scribe line areas between the chip die areas, the scribe line areas including one or more second sets of polygonal structures. The presence of proximate polygonal structures between the scribe line and seal ring areas balance stresses between the chip die areas during wafer dicing operation.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: October 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Pin Cheng, Jung-Liang Chien, Chih-Kang Chao, Chi-Cherng Jeng, Hsin-Chi Chen, Ying-Lang Wang
  • Publication number: 20140167199
    Abstract: A semiconductor wafer having a plurality of chip die areas arranged on a wafer in an array, each chip die area including a seal ring area with one or more first sets of polygonal structures. The wafer further comprises scribe line areas between the chip die areas, the scribe line areas including one or more second sets of polygonal structures. The presence of proximate polygonal structures between the scribe line and seal ring areas balance stresses between the chip die areas during wafer dicing operation.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Pin CHENG, Jung-Liang CHIEN, Chih-Kang CHAO, Chi-Cherng JENG, Hsin-Chi CHEN, Ying-Lang WANG
  • Publication number: 20090135333
    Abstract: The invention discloses an LCD with an ambient light sense function and its method. The method compraises the step of: coupling a capacitor to a source electrode of a thin film transistor; calculating a transmission time which required by a potential change from the reduction of electric charges; and finally, calculating an intensity of the ambient light according to the transmission time. The invention further discloses an ambient light sense circuit having a thin film transistor, a capacitor and a read-out switch. As the ambient light changes, a leakage current of the thin film transistor is changed accordingly, and the transmission time which required by the potential change is therefore changed. The read-out switch transmits said potential to a data read-out line in order to calculate the intensity of the ambient light from the transmission time. The LCD of this invention includes a plurality of capacitors, a plurality of read-out switches and a processing module.
    Type: Application
    Filed: March 6, 2008
    Publication date: May 28, 2009
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Ya-Hsiang Tai, Han-Ching Ho, Chia-Pin Cheng