Patents by Inventor Chia-Pin Lin

Chia-Pin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11119294
    Abstract: An optical system includes a fixed module, a movable module and a driving assembly. The movable module moves relative to the fixed module, and the movable module includes a lens unit which includes a first lens, a second lens, a first side wall and a second side wall. The first side wall has a first surface, which directly contacts the second lens, and the second side wall directly contacts the first lens. A portion of the driving assembly is directly disposed on the lens unit, configured to drive the lens unit to move along an optical axis of the first lens. The first side wall further has a second surface opposite to the first surface, and the second surface directly contacts the portion of the driving assembly. The thickness of the first side wall is different from the thickness of the second side wall.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: September 14, 2021
    Assignee: TDK TAIWAN CORP.
    Inventors: Chih-Wei Weng, Chia-Pin Hsu, Shao-Kuang Huang, Kun-Shih Lin, Shou-Jen Liu, Sin-Jhong Song
  • Publication number: 20210272848
    Abstract: A method includes etching two source/drain regions over a substrate to form two source/drain trenches; epitaxially growing two source/drain features in the two source/drain trenches respectively; performing a cut process to the two source/drain features; and after the cut process, depositing a contact etch stop layer (CESL) over the two source/drain features.
    Type: Application
    Filed: May 29, 2020
    Publication date: September 2, 2021
    Inventors: Feng-Ching Chu, Wei-Yang Lee, Chia-Pin Lin
  • Publication number: 20210273114
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.
    Type: Application
    Filed: December 18, 2020
    Publication date: September 2, 2021
    Inventors: Ting-Yeh Chen, Wei-Yang Lee, Chia-Pin Lin
  • Publication number: 20210273103
    Abstract: A method includes providing a structure having a substrate and a fin. The fin has first and second layers of first and second different semiconductor materials. The first layers and the second layers are alternately stacked over the substrate. The structure further has a sacrificial gate stack engaging a channel region of the fin and gate spacers on sidewalls of the sacrificial gate stack. The method further includes etching a source/drain (S/D) region of the fin, resulting in an S/D trench; partially recessing the second layers exposed in the S/D trench, resulting in a gap between two adjacent layers of the first layers; and depositing a dielectric layer over surfaces of the gate spacers, the first layers, and the second layers. The dielectric layer partially fills the gap, leaving a void sandwiched between the dielectric layer on the two adjacent layers of the first layers.
    Type: Application
    Filed: July 31, 2020
    Publication date: September 2, 2021
    Inventors: Shih-Chiang Chen, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
  • Patent number: 11106000
    Abstract: A driving mechanism for supporting an optical member is provided, including a base, a frame, a movable portion, a driving module, and an adhesive member. The base includes a plurality of first sidewalls, and at least one recess is formed on the first sidewalls. The frame includes a plurality of second sidewalls, and at least one opening is formed on the second sidewalls. The base and the frame form a hollow box, and the opening corresponds to the recess. The movable portion and the driving module are disposed in the hollow box. The driving module can drive the movable portion to move relative to the base. The adhesive member is accommodated in the opening and the recess, and extended along the first sidewalls. The adhesive member is disposed between the first sidewalls and the second sidewalls.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: August 31, 2021
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Publication number: 20190181048
    Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.
    Type: Application
    Filed: February 8, 2019
    Publication date: June 13, 2019
    Inventors: Chia-Pin LIN, Chien-Tai CHAN, Hsien-Chin LIN, Shyue-Shyh LIN
  • Patent number: 10224245
    Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: March 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Pin Lin, Chien-Tai Chan, Hsien-Chin Lin, Shyue-Shyh Lin
  • Patent number: 10118457
    Abstract: An anti-roll bar device with a variable rigidity has a first arm assembly having multiple first joining units, a second arm assembly having multiple second joining units, and a variable rigidity unit mounted between the first arm assembly and the second arm assembly and having multiple abutment portions and a variable rigidity coefficient. The first and second joining units are staggered with each other annularly and abut the abutment portions. When a vehicle passes a bumpy terrain, a slight force is exerted on the variable rigidity unit and is absorbed by the variable rigidity unit, such that the vehicle can be kept from tilting and shaking up and down. When the vehicle is in cornering, a larger force is exerted on the variable rigidity unit to increase a rigidity of the variable rigidity unit, such that the variable rigidity unit can transfer torques to keep the vehicle from tilting.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: November 6, 2018
    Assignee: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Chun-Pin Yang, Chia Pin Lin, Wei Lun Hsu
  • Publication number: 20170106714
    Abstract: An anti-roll bar device with a variable rigidity has a first arm assembly having multiple first joining units, a second arm assembly having multiple second joining units, and a variable rigidity unit mounted between the first arm assembly and the second arm assembly and having multiple abutment portions and a variable rigidity coefficient. The first and second joining units are staggered with each other annularly and abut the abutment portions. When a vehicle passes a bumpy terrain, a slight force is exerted on the variable rigidity unit and is absorbed by the variable rigidity unit, such that the vehicle can be kept from tilting and shaking up and down. When the vehicle is in cornering, a larger force is exerted on the variable rigidity unit to increase a rigidity of the variable rigidity unit, such that the variable rigidity unit can transfer torques to keep the vehicle from tilting.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 20, 2017
    Applicant: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTRE
    Inventors: Chun-Pin YANG, Chia Pin LIN, Wei Lun HSU
  • Publication number: 20160204255
    Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.
    Type: Application
    Filed: March 22, 2016
    Publication date: July 14, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Pin LIN, Chien-Tai CHAN, Hsien-Chin LIN, Shyue-Shyh LIN
  • Patent number: 9349657
    Abstract: A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: May 24, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Hsiung Wang, Hsien-Chin Lin, Yuan-Ching Peng, Chia-Pin Lin, Fan-Yi Hsu, Ya-Jou Hsieh
  • Patent number: 9312179
    Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: April 12, 2016
    Assignee: Taiwan-Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Pin Lin, Chien-Tai Chan, Hsien-Chin Lin, Shyue-Shyh Lin
  • Patent number: 9281307
    Abstract: A semiconductor device which includes a first gate structure on a substrate and a second gate structure on the substrate is provided. The semiconductor device further includes an inter-level dielectric (ILD) layer on the substrate between the first gate structure and the second gate structure, wherein a top portion of the ILD layer has a different etch selectivity than a bottom portion of the ILD layer.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: March 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Chia-Pin Lin, Sheng-Hsiung Wang, Fan-Yi Hsu, Chun-Liang Tai
  • Patent number: 9281356
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Da-Wen Lin, Kuo-Feng Yu
  • Patent number: 9224737
    Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Kai Chen, Hsien-Hsin Lin, Chia-Pin Lin, Chien-Tai Chan, Yuan-Ching Peng
  • Publication number: 20150115322
    Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.
    Type: Application
    Filed: November 26, 2014
    Publication date: April 30, 2015
    Inventors: Hung-Kai CHEN, Hsien-Hsin LIN, Chia-Pin LIN, Chien-Tai CHAN, Yuan-Ching PENG
  • Publication number: 20150111361
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 23, 2015
    Inventors: King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Da-Wen Lin, Kuo-Feng Yu
  • Patent number: 8994116
    Abstract: Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tian-Choy Gan, Hsien-Chin Lin, Chia-Pin Lin, Shyue-Shyh Lin, Li-Shiun Chen, Shin Hsien Liao
  • Patent number: 8937353
    Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: January 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Kai Chen, Hsien-Hsin Lin, Chia-Pin Lin, Chien-Tai Chan, Yuan-Ching Peng
  • Patent number: 8921946
    Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: King-Yuen Wong, Chia-Pin Lin, Chia-Yu Lu, Yi-Cheng Tsai, Da-Wen Lin, Kuo-Feng Yu