Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.

Abstract: Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.

Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.

Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.

Abstract: A charge/discharge circuit is configured to directly charge a storage system using a power source under a power-on stage and to charge the storage system using power pre-stored in a capacitor under a power-off stage. With the aid of the charge/discharge circuit, an access speed of the storage system is prevented from being slowed down by attaching the large capacitance of the capacitor, and data accuracy of the storage system is prevented from being affected by sudden loss of power supply of the power source.

Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.

Abstract: A transistor includes a notched fin covered under a shallow trench isolation layer. One or more notch may be used, the size of which may vary along a lateral direction of the fin. In some embodiments, The notch is formed using anisotropic wet etching that is selective according to silicon orientation. Example wet etchants are tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH).

Abstract: An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer.

Abstract: Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.

Abstract: Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.

Abstract: A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection adjacent the first channel region. The first gate structure includes a first dielectric material over the first channel region, a first opening over the first dielectric material and the first channel region, and a pure first metal with an n-type work function value conformally deposited in the first opening. The device also includes a second gate structure engaging the second projection adjacent the second channel region. The second gate structure includes a second dielectric material over the second channel region, a second opening over the second dielectric material and the second channel region, and a pure second metal with a p-type work function value conformally deposited in the second opening.

Abstract: A semiconductor device which includes a first gate structure on a substrate and a second gate structure on the substrate is provided. The semiconductor device further includes an inter-level dielectric (ILD) layer on the substrate between the first gate structure and the second gate structure, wherein a top portion of the ILD layer has a different etch selectivity than a bottom portion of the ILD layer.

Abstract: A semiconductor device includes a substrate including an isolation region, and a resistor disposed over the isolation region, wherein the resistor includes an implant with an inverse box-like dopant profile that minimizes resistance variation from subsequent planarization variation. A contact is disposed over the resistor. A method of fabricating such a semiconductor device is also provided.

Abstract: An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.

Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD0, surrounding the gate structures with a dopant to reduce its etch rates during the processes of removing dummy gate electrode layer and/or gate dielectric layer for replacement gate technologies. The ILD0 film may be doped with a plasma doping process (PLAD) or an ion beam process. Post doping anneal is optional.

Abstract: An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer.

Abstract: An apparatus includes a first device. The first device includes a first projection and a first gate structure, the first projection extending upwardly from a substrate and having a first channel region therein, and the first gate structure engaging the first projection adjacent the first channel region. The first structure includes an opening over the first channel region, and a conformal, pure metal with a low resistivity disposed in the opening. The apparatus also includes a second device that includes a second projection and a second gate structure, the second projection extending upwardly from the substrate and having a second channel region therein, and the second gate structure engaging the second projection adjacent the second channel region. The second structure includes a silicide disposed over the second channel region, wherein the silicide includes a metal that is the same metal disposed in the opening.

Abstract: A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.

Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD0, surrounding the gate structures with a dopant to reduce its etch rates during the processes of removing dummy gate electrode layer and/or gate dielectric layer for replacement gate technologies. The ILD0 film may be doped with a plasma doping process (PLAD) or an ion beam process. Post doping anneal is optional.