Patents by Inventor Chia Ping Lo
Chia Ping Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 10861751Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate, and forming a first layer including a first material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer, wherein performing the anneal process includes adjusting an energy applied to the first layer during the anneal process. The gap is filled by a portion of the first material around the gap reaching a sub-melt temperature that is different from a melting point of the first material.Type: GrantFiled: November 18, 2019Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: De-Wei Yu, Chia Ping Lo, Liang-Gi Yao, Weng Chang, Yee-Chia Yeo, Ziwei Fang
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Publication number: 20200083112Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate, and forming a first layer including a first material over the first and second fin elements, wherein the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer, wherein performing the anneal process includes adjusting an energy applied to the first layer during the anneal process. The gap is filled by a portion of the first material around the gap reaching a sub-melt temperature that is different from a melting point of the first material.Type: ApplicationFiled: November 18, 2019Publication date: March 12, 2020Inventors: De-Wei YU, Chia Ping LO, Liang-Gi YAO, Weng CHANG, Yee-Chia YEO, Ziwei FANG
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Patent number: 10522631Abstract: A semiconductor device includes a transistor having a source/drain region. A conductive contact is disposed over the source/drain region. A silicide element is disposed below the conductive contact. The silicide element has a non-angular cross-sectional profile. In some embodiments, the silicide element may have an approximately curved cross-sectional profile, for example an ellipse-like profile. The silicide element is formed at least in part by forming an amorphous region in the source/drain region via an implantation process. The implantation process may be a cold implantation process.Type: GrantFiled: July 23, 2018Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Wen Chen, Shih Yu-Shen, Chia Ping Lo, Yan-Hua Lin, Lun-Kuang Tan, Yu-Ting Lin
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Patent number: 10483170Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer including an amorphous material is formed over the first and second fin elements, where the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer. The amorphous material of the first layer remains amorphous during the performing of the anneal process.Type: GrantFiled: June 25, 2018Date of Patent: November 19, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: De-Wei Yu, Chia Ping Lo, Liang-Gi Yao, Weng Chang, Yee-Chia Yeo, Ziwei Fang
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Publication number: 20180350924Abstract: A semiconductor device includes a transistor having a source/drain region. A conductive contact is disposed over the source/drain region. A silicide element is disposed below the conductive contact. The silicide element has a non-angular cross-sectional profile. In some embodiments, the silicide element may have an approximately curved cross-sectional profile, for example an ellipse-like profile. The silicide element is formed at least in part by forming an amorphous region in the source/drain region via an implantation process. The implantation process may be a cold implantation process.Type: ApplicationFiled: July 23, 2018Publication date: December 6, 2018Inventors: Sheng-Wen Chen, Shih Yu-Shen, Chia Ping Lo, Yan-Hua Lin, Lun-Kuang Tan, Yu-Ting Lin
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Publication number: 20180308765Abstract: A method includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer including an amorphous material is formed over the first and second fin elements, where the first layer includes a gap disposed between the first and second fin elements. An anneal process is performed to remove the gap in the first layer. The amorphous material of the first layer remains amorphous during the performing of the anneal process.Type: ApplicationFiled: June 25, 2018Publication date: October 25, 2018Inventors: De-Wei YU, Chia Ping LO, Liang-Gi YAO, Weng CHANG, Yee-Chia YEO, Ziwei FANG
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Patent number: 10032876Abstract: A semiconductor device includes a transistor having a source/drain region. A conductive contact is disposed over the source/drain region. A silicide element is disposed below the conductive contact. The silicide element has a non-angular cross-sectional profile. In some embodiments, the silicide element may have an approximately curved cross-sectional profile, for example an ellipse-like profile. The silicide element is formed at least in part by forming an amorphous region in the source/drain region via an implantation process. The implantation process may be a cold implantation process.Type: GrantFiled: March 13, 2014Date of Patent: July 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Wen Chen, Shih Yu-Shen, Chia Ping Lo, Yan-Hua Lin, Lun-Kuang Tan, Yu-Ting Lin
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Patent number: 10008418Abstract: A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to the substrate to remove the gap in the first layer. An energy applied to the first layer during the laser anneal process is adjusted based on a height of the first layer.Type: GrantFiled: September 30, 2016Date of Patent: June 26, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: De-Wei Yu, Chia-Ping Lo, Liang-Gi Yao, Weng Chang, Yee-Chia Yeo, Ziwei Fang
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Publication number: 20180096898Abstract: A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the substrate. A first layer is formed over the first and second fin elements, where the first layer includes a gap. A laser anneal process is performed to the substrate to remove the gap in the first layer. An energy applied to the first layer during the laser anneal process is adjusted based on a height of the first layer.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: De-Wei YU, Chia-Ping LO, Liang-Gi YAO, Weng CHANG, Yee-Chia YEO, Ziwei FANG
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Patent number: 9496367Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate. The metal gate stack is between the source region and the drain region. The insulating layer surrounds the metal gate stack. The method includes forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively. The method includes performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings. The method includes after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings. The dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively.Type: GrantFiled: December 22, 2015Date of Patent: November 15, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-Chun Wang, Yi-Chun Lo, Chia-Der Chang, Guo-Chiang Chi, Chia-Ping Lo, Fu-Kai Yang, Hung-Chang Hsu, Mei-Yun Wang
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Publication number: 20160118471Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, a metal gate stack, and an insulating layer formed over the semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate. The metal gate stack is between the source region and the drain region. The insulating layer surrounds the metal gate stack. The method includes forming contact openings passing through the insulating layer to expose the source region and the drain region, respectively. The method includes performing a first pre-amorphized implantation process to form amorphous regions in the source region and the drain region exposed by the contact openings. The method includes after the first pre-amorphized implantation process, forming a dielectric spacer liner layer over sidewalls of the contact openings. The dielectric spacer liner layer has holes exposing portions of the amorphous regions, respectively.Type: ApplicationFiled: December 22, 2015Publication date: April 28, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tien-Chun WANG, Yi-Chun LO, Chia-Der CHANG, Guo-Chiang CHI, Chia-Ping LO, Fu-Kai YANG, Hung-Chang HSU, Mei-Yun WANG
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Patent number: 9231098Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively. The semiconductor device further includes a metal gate stack formed over the semiconductor substrate and between the source region and the drain region. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively. The semiconductor device includes a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions. The semiconductor device includes contact plugs formed in the contact openings.Type: GrantFiled: October 30, 2013Date of Patent: January 5, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tien-Chun Wang, Yi-Chun Lo, Chia-Der Chang, Guo-Chiang Chi, Chia-Ping Lo, Fu-Kai Yang, Hung-Chang Hsu, Mei-Yun Wang
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Publication number: 20150263109Abstract: A semiconductor device includes a transistor having a source/drain region. A conductive contact is disposed over the source/drain region. A silicide element is disposed below the conductive contact. The silicide element has a non-angular cross-sectional profile. In some embodiments, the silicide element may have an approximately curved cross-sectional profile, for example an ellipse-like profile. The silicide element is formed at least in part by forming an amorphous region in the source/drain region via an implantation process. The implantation process may be a cold implantation process.Type: ApplicationFiled: March 13, 2014Publication date: September 17, 2015Inventors: Sheng-Wen Chen, Shih Yu-Shen, Chia Ping Lo, Yan-Hua Lin, Lun-Kuang Tan, Yu-Ting Lin
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Publication number: 20150115335Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively. The semiconductor device further includes a metal gate stack formed over the semiconductor substrate and between the source region and the drain region. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively. The semiconductor device includes a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions. The semiconductor device includes contact plugs formed in the contact openings.Type: ApplicationFiled: October 30, 2013Publication date: April 30, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Tien-Chun WANG, Yi-Chun LO, Chia-Der CHANG, Guo-Chiang CHI, Chia-Ping LO, Fu-Kai YANG, Hung-Chang HSU, Mei-Yun WANG
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Patent number: 7795119Abstract: A structure and a method for mitigation of the damage arising in the source/drain region of a MOSFET is presented. A substrate is provided having a gate structure comprising a gate oxide layer and a gate electrode layer, and a source and drain region into which impurity ions have been implanted. A PAI process generates an amorphous layer within the source and drain region. A metal is deposited and is reacted to create a silicide within the amorphous layer, without exacerbating existing defects. Conductivity of the source and drain region is then recovered by flash annealing the substrate.Type: GrantFiled: July 17, 2007Date of Patent: September 14, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia Ping Lo, Jerry Lai, Chii-Ming Wu, Mei-Yun Wang, Da-Wen Lin
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Publication number: 20090020757Abstract: A structure and a method for mitigation of the damage arising in the source/drain region of a MOSFET is presented. A substrate is provided having a gate structure comprising a gate oxide layer and a gate electrode layer, and a source and drain region into which impurity ions have been implanted. A PAI process generates an amorphous layer within the source and drain region. A metal is deposited and is reacted to create a silicide within the amorphous layer, without exacerbating existing defects. Conductivity of the source and drain region is then recovered by flash annealing the substrate.Type: ApplicationFiled: July 17, 2007Publication date: January 22, 2009Inventors: Chia Ping Lo, Jerry Lai, Chii-Ming Wu, Mei-Yun Wang, Da-Wen Lin