Patents by Inventor Chia Rung Hsu

Chia Rung Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150253917
    Abstract: The present invention relates to a touch panel, a display panel, and a strengthened structure for a protective substrate, wherein the touch panel comprises: a touch sensing layer; a buffer layer disposed over the touch sensing layer and having a first surface and a second surface, wherein the second surface faces towards the touch sensing layer; and a protective substrate disposed on the first surface of the buffer layer.
    Type: Application
    Filed: March 4, 2015
    Publication date: September 10, 2015
    Inventors: Chia-Fu FAN, Tsu-Hsien KU, Chia-Rung HSU, Jing-Jia YEH
  • Patent number: 7294575
    Abstract: A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: November 13, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Rung Hsu, Art Yu, Hsiao-Ling Lu, Teng-Chun Tsai
  • Patent number: 7172970
    Abstract: A polish method for planarization is disclosed. The method uses a combination of a traditional oxide CMP and HSP-CMP (High Selectivity and Planarization) with a fix abrasive pad to meet the requirements of the CMP process for a device feature dimension under 0.18 micron even to 0.09 micron. By using a first polish step with a conventional polish pad and an oxide polish slurry, the non-uniformity of the over-fill thickness of the STI dielectric layer can be firstly removed and a much more smooth and uniform topography favorable for the HSP-CMP process the fix abrasive polishing pad can be obtained. Then the HSP-CMP process with the fix abrasive polishing pad can be performed to provide a planarized surface with accurate dimension control.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: February 6, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Zong Huei Lin, Art Yu, Chia Rung Hsu, Teng-Chun Tsai
  • Publication number: 20050148184
    Abstract: A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.
    Type: Application
    Filed: January 5, 2004
    Publication date: July 7, 2005
    Inventors: Chia-Rung Hsu, Art Yu, Hsiao-Ling Lu, Teng-Chun Tsai
  • Publication number: 20050101233
    Abstract: A polishing element comprising a polishing platen, a polishing sub-pad and a polishing pad is provided. The polishing sub-pad is set up over the polishing platen and the polishing pad is set up over the polishing sub-pad. A first surface of the polishing sub-pad interfaces with the polishing pad and a second surface of the polishing sub-pad interfaces with the platen. Either the first surface or the second surface of the polishing sub-pad is an undulating surface.
    Type: Application
    Filed: November 19, 2003
    Publication date: May 12, 2005
    Inventors: Teng-Chun Tsai, Chia-Rung Hsu, Art Yu, Gene Li
  • Publication number: 20040180546
    Abstract: A polish method for planarization is disclosed. The method uses a combination of a traditional oxide CMP and HSP-CMP (High Selectivity and Planarization) with a fix abrasive pad to meet the requirements of the CMP process for a device feature dimension under 0.18 micron even to 0.09 micron. By using a first polish step with a conventional polish pad and an oxide polish slurry, the non-uniformity of the over-fill thickness of the STI dielectric layer can be firstly removed and a much more smooth and uniform topography favorable for the HSP-CMP process the fix abrasive polishing pad can be obtained. Then the HSP-CMP process with the fix abrasive polishing pad can be performed to provide a planarized surface with accurate dimension control.
    Type: Application
    Filed: March 11, 2003
    Publication date: September 16, 2004
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Zong Huei Lin, Art Yu, Chia Rung Hsu, Teng-Chun Tsai