Abstract: An integrated circuit identification device (10) includes a plurality of inverters (12-16), a first bus (24), an address bus (26), a plurality of drivers (18-22), a pre-charge circuit (28) and an identification code access (30). Each inverter (12) includes a P-channel FET (32-36) and an N-channel FET (38). An identification code is written to the device (10) by selectively breaking down the gate-well dielectric layer (112) of the N-channel FET which permanently alters the FET. When the address bus provides a read signal to the gate drivers, each N-channel FET that has been altered will be unable to turn on, thus the precharging of the P-channel FET keeps the output of the inverter at a logic "1". N-channel FETs that have not be altered will be on when the read signal is provided, thus providing a logic "0".