Patents by Inventor Chia-Sheng Chou
Chia-Sheng Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103342Abstract: A variable aperture module includes a blade assembly, a positioning element, a driving part and pressing structures. The blade assembly includes movable blades disposed around an optical axis to form a light passable hole with an adjustable size. Each movable blade has a positioning hole and a movement hole adjacent thereto. The positioning element includes positioning structures disposed respectively corresponding to the positioning holes. The driving part includes a rotation element disposed corresponding to the movement holes and is rotatable with respect to the positioning element. The pressing structures are disposed respectively corresponding to the movable blades. Each pressing structure is at least disposed into at least one of the positioning hole and the movement hole of the corresponding movable blade. Each pressing structure at least presses against at least one of the corresponding one positioning structure and the rotation element.Type: ApplicationFiled: November 21, 2022Publication date: March 28, 2024Applicant: LARGAN PRECISION CO., LTD.Inventors: Chia-Cheng TSAI, Hsiu-Yi HSIAO, Ming-Ta CHOU, Te-Sheng TSENG
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Publication number: 20240071537Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Inventors: Meng-Sheng Chang, Chia-En Huang, Shao-Yu Chou, Yih Wang
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Publication number: 20200244289Abstract: A data writing method, a memory control circuit unit and a memory storage device are provided. The method includes: executing a first programming operation to data according to a first RAID ECC rate, programming the data into at least a portion of a plurality of first physical programming units, and generating a first RAID ECC; and executing a second programming operation to the data programmed into at least the portion of the first physical programming units according to a second RAID ECC rate, programming the data into at least a portion of a plurality of second physical programming units, and generating a second RAID ECC, wherein the first RAID ECC rate is different from the second RAID ECC rate.Type: ApplicationFiled: March 20, 2019Publication date: July 30, 2020Applicant: PHISON ELECTRONICS CORP.Inventors: Chia-Sheng Chou, Chia-Cheng Tu, Kuo-Ming Tseng, Yi-Liang Hu
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Patent number: 10713160Abstract: A data writing method, a memory control circuit unit and a memory storage device are provided. The method includes: executing a first programming operation to data according to a first RAID ECC rate, programming the data into at least a portion of a plurality of first physical programming units, and generating a first RAID ECC; and executing a second programming operation to the data programmed into at least the portion of the first physical programming units according to a second RAID ECC rate, programming the data into at least a portion of a plurality of second physical programming units, and generating a second RAID ECC, wherein the first RAID ECC rate is different from the second RAID ECC rate.Type: GrantFiled: March 20, 2019Date of Patent: July 14, 2020Assignee: PHISON ELECTRONICS CORP.Inventors: Chia-Sheng Chou, Chia-Cheng Tu, Kuo-Ming Tseng, Yi-Liang Hu
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Patent number: 8510508Abstract: Method for accessing data in a storage system architecture, the architecture comprises at least one disk array subsystem, comprising the following steps. Provide a SAS for managing a first and a second media extent (ME) the at least one subsystem. Obtain a location index corresponding to a host LBA via a BAT. Obtain a location information of a physical section located in the first ME corresponding to the location index via a physical section to virtual section cross-referencing functionality. Update the cross-reference in the cross-referencing functionality so that the location information obtained from the cross-referencing functionality corresponding to the location index is the location information of the second physical section. A host IO request addressing the host LBA accesses data in the second physical section utilizing the location information of the second physical section.Type: GrantFiled: January 22, 2010Date of Patent: August 13, 2013Assignee: Infortrend Technology, Inc.Inventors: Michael Gordon Schnapp, Ching-Hua Fang, Chia-Sheng Chou
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Publication number: 20100199041Abstract: Method for accessing data in a storage system architecture, the architecture comprises at least one disk array subsystem, comprising the following steps. Provide a SAS for managing a first and a second media extent (ME) the at least one subsystem. Obtain a location index corresponding to a host LBA via a BAT. Obtain a location information of a physical section located in the first ME corresponding to the location index via a physical section to virtual section cross-referencing functionality. Update the cross-reference in the cross-referencing functionality so that the location information obtained from the cross-referencing functionality corresponding to the location index is the location information of the second physical section. A host IO request addressing the host LBA accesses data in the second physical section utilizing the location information of the second physical section.Type: ApplicationFiled: January 22, 2010Publication date: August 5, 2010Applicant: INFORTREND TECHNOLOGY, INC.Inventors: Michael Gordon Schnapp, Ching-Hua FANG, Chia-Sheng CHOU
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Patent number: 6317515Abstract: An encoding/decoding method and apparatus encodes an input data stream for compression purposes, and decodes the compressed data stream for use. The encoding process identifies trends in the data stream, and stores information about the trends in an encoded block. The trends may include runs, in which sequential, corresponding gropus in the data stream have constant values. The trends may also include ramps, where sequential, corresponging components in the data stream increase or decrease by a linear value. An encoded block may also be provided to transfer raw data. The encoded blocks do not store type information describing the type of the component associated with the block. Rather, the decoder infers the type of the components associated with the encoded block according to an original order of components in the data stream, the order of the encoded block in the sequence of encoded blocks and a number of the corresponding components encoded by each of the preceding encoded blocks.Type: GrantFiled: April 3, 1998Date of Patent: November 13, 2001Assignee: Avid Technology, Inc.Inventors: Jeffrey D. Kurtze, Joseph H. Rice, Robert Gonsalves, Chia-Sheng Chou
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Patent number: 6269195Abstract: A mechanism and process for feathering a first image and a second image in a composite image includes defining an original matte image. A portion of the original matte image is box filtered horizontally and vertically to generate an intermediate matte image. At least a portion of the intermediate matte image is box filtered horizontally and vertically to generate a processed matte image. An edge biasing function is applied to the processed matte image. Edge biasing includes further modifying pixel values on an edge by changing the contrast and brightness of the matte image. A composite image including the first image and the second image is then generated after applying the edge biasing function to the box-filtered processed matte image.Type: GrantFiled: February 3, 1998Date of Patent: July 31, 2001Assignee: Avid Technology, Inc.Inventors: Robert Gonsalves, Chia-Sheng Chou
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Patent number: 6201531Abstract: The invention provides a mechanism and process for changing a color of an image. In this process, a source frame that includes the image is received. An alpha matte that covers an object in the source frame is created. An original color of a pixel in the source frame is changed when the pixel is covered by the alpha matte, and when a color distance between the original color of the pixel and a target color is below a predetermined threshold.Type: GrantFiled: July 10, 2000Date of Patent: March 13, 2001Assignee: Avid Technology, Inc.Inventors: Robert Gonsalves, Chia-Sheng Chou, Brian C. Cooper, Dion C. Scoppettuolo
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Patent number: 6137919Abstract: The invention provides a mechanism and process for feathering a first image and a second image in a composite frame. In this process an original matte image is defined according to the first and second images. A portion of the original matte image is box filtered horizontally and vertically to generate an intermediate matte image. At least a portion of the intermediate matte image is box filtered horizontally and vertically to generate a processed matte image. A composite image including the first image and the second image is then generated according to the box-filtered processed matte image.Type: GrantFiled: April 4, 1997Date of Patent: October 24, 2000Assignee: Avid Technology, Inc.Inventors: Robert Gonsalves, Chia-Sheng Chou
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Patent number: 6128001Abstract: The invention provides a mechanism and process for changing a color of an image. In this process, a source frame that includes the image is received. An alpha matte that covers an object in the source frame is created. An original color of a pixel in the source frame is changed when the pixel is covered by the alpha matte, and when a color distance between the original color of the pixel and a target color is below a predetermined threshold.Type: GrantFiled: April 4, 1997Date of Patent: October 3, 2000Assignee: Avid Technology, Inc.Inventors: Robert Gonsalves, Chia-Sheng Chou, Brian C. Cooper, Dion C. Scoppettuolo