Patents by Inventor Chia-Sheng Ho

Chia-Sheng Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240162833
    Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
  • Patent number: 11942380
    Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Shiang Lin, Chia-Cheng Ho, Chun-Chieh Lu, Cheng-Yi Peng, Chih-Sheng Chang
  • Patent number: 6548332
    Abstract: A process for forming a thin film transistor includes steps of (a) forming a gate on a portion of a substrate, (b) forming a gate dielectric layer, a semiconductor layer, a source, a drain, and a passivation in order on the substrate, and (c) proceeding a thermal treatment under atmosphere of a specific assistant gas. The specific assistant gas is one selected from a group consisting of hydrogen, steam, inert gases, and gas mixtures thereof. After providing the specific assistant gas during the thermal treatment, the process can improve the output property of the thin film transistor for avoiding double hump phenomenon.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: April 15, 2003
    Assignee: Hannstar Display Corp.
    Inventors: Chih-Yu Peng, Chia-Sheng Ho, Shih-Ming Chen, In-Cha Hsieh
  • Publication number: 20020048867
    Abstract: A process for forming a thin film transistor includes steps of (a) forming a gate on a portion of a substrate, (b) forming a gate dielectric layer, a semiconductor layer, a source, a drain, and a passivation in order on the substrate, and (c) proceeding a thermal treatment under atmosphere of a specific assistant gas. The specific assistant gas is one selected from a group consisting of hydrogen, steam, inert gases, and gas mixtures thereof. After providing the specific assistant gas during the thermal treatment, the process can improve the output property of the thin film transistor for avoiding double hump phenomenon.
    Type: Application
    Filed: April 20, 2001
    Publication date: April 25, 2002
    Applicant: HANNSTAR DISPLAY CORP
    Inventors: Chih-Yu Peng, Chia-Sheng Ho, Shih-Ming Chen, In-Cha Hsieh
  • Patent number: D486458
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: February 10, 2004
    Assignee: High Tech Computer, Corp.
    Inventors: Cheng-Lun Chen, Chia-Sheng Ho