Patents by Inventor Chia-Shia Tsai

Chia-Shia Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6995085
    Abstract: A method of protecting an underlying diffusion barrier layer in a dual damascene trench and via etch process with a coating of negative photoresist. The dual damascene process starts with via hole etching in an intermetal dielectric (IMD) layer. Next, the thin film barrier layer is deposited and patterned to fill the bottom of the vias. The key process step is a coating of negative photoresist which is exposed and developed to partially fill the via openings. This thick layer of negative photoresist in the vias protects the thin diffusion barrier layer from subsequent dual damascene etch processing.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: February 7, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lawrence Lui, Chia-Shia Tsai, Chao-Cheng Chen, Jen-Cheng Liu
  • Publication number: 20040142554
    Abstract: A method of protecting an underlying diffusion barrier layer in a dual damascene trench and via etch process with a coating of negative photoresist. The dual damascene process starts with via hole etching in an intermetal dielectric (IMD) layer. Next, the thin film barrier layer is deposited and patterned to fill the bottom of the vias. The key process step is a coating of negative photoresist which is exposed and developed to partially fill the via openings. This thick layer of negative photoresist in the vias protects the thin diffusion barrier layer from subsequent dual damascene etch processing.
    Type: Application
    Filed: January 17, 2003
    Publication date: July 22, 2004
    Applicant: Taiwan Semiconductor Manufacturing Company
    Inventors: Lawrence Lui, Chia-Shia Tsai, Chao-Cheng Chen, Jen-Cheng Liu
  • Patent number: 6297168
    Abstract: Within a method for etching a trench within a silicon oxide layer there is first provided a substrate. There is then formed over the substrate a silicon oxide layer. There is then formed over the silicon oxide layer a masking layer. There is then etched, while employing a plasma etch method in conjunction with the masking layer as an etch mask layer, the silicon oxide layer to form an etched silicon oxide layer defining a trench. Within the method, the plasma etch method employs an etchant gas composition comprising: (1) octafluorocyclobutane; and (2) at least one of carbon tetrafluoride, difluoromethane, hexafluoroethane and oxygen; but excluding (3) a carbon and oxygen containing gas.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: October 2, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Jyu-Horng Shieh, Jen-Cheng Liu, Chao-Cheng Chen, Li-Chi Chao, Chia-Shia Tsai
  • Patent number: 6211063
    Abstract: A method to form dual damascene structures is described. A first silicon oxynitride layer is deposited overlying a provided substrate. A silicate glass layer is deposited overlying the first silicon oxynitride. A second silicon oxynitride layer is deposited overlying the silicate glass. Photoresist is deposited overlying the second silicon oxynitride and is etched to define areas of planned lower trenches. The second silicon oxynitride layer is etched to expose the top surface of the silicate glass layer. The remaining photoresist layer is etched away. An hydrogen silsesquioxane layer is deposited overlying the second silicon oxynitride and the silicate glass. An oxide layer is deposited overlying the hydrogen silsesquioxane. Photoresist is deposited overlying the oxide and is etched to define areas of planned upper trenches. The oxide layer and the hydrogen silsesquioxane layer are etched by reactive ion etching by a recipe comprising C4F8, CO, Ar, and N2 gases to form the upper trenches.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: April 3, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Jen-Cheng Liu, Chia-Shia Tsai