Patents by Inventor Chia-Shiung Tsia

Chia-Shiung Tsia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6803291
    Abstract: A method for protecting an alignment mark area during a CMP process including forming at least a first material layer over a process surface of a semiconductor wafer including active areas and alignment mark trenches formed in the at least one alignment mark area; forming at least a second material layer over the first material layer including the active areas and the at least one alignment mark area; lithographically patterning and etching the at least a second material layer to form at least a plurality lines of the at least a second material layer adjacent to the alignment mark trenches; and, carrying out a CMP process to remove at least a portion of the at least a second material layer.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: October 12, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Shih-Chi Fu, Feng-Jia Shih, Chia-Tung Ho, Chih-Ta Wu, Ching-Sen Kuo, Jieh-Jang Chen, Gwo-Yuh Shiau, Chia-Shiung Tsia
  • Publication number: 20040185637
    Abstract: A method for protecting an alignment mark area during a CMP process including forming at least a first material layer over a process surface of a semiconductor wafer including active areas and alignment mark trenches formed in the at least one alignment mark area; forming at least a second material layer over the first material layer including the active areas and the at least one alignment mark area; lithographically patterning and etching the at least a second material layer to form at least a plurality lines of the at least a second material layer adjacent to the alignment mark trenches; and, carrying out a CMP process to remove at least a portion of the at least a second material layer.
    Type: Application
    Filed: March 20, 2003
    Publication date: September 23, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.,
    Inventors: Shih-Chi Fu, Feng-Jia Shiu, Chia-Tung Ho, Chih-Ta Wu, Ching-Sen Kuo, Jieh-Jang Chen, Gwo-Yuh Shiau, Chia-Shiung Tsia
  • Patent number: 6645851
    Abstract: A method of forming a planarized photoresist coating on a substrate having holes with different duty ratios is described. A first photoresist preferably comprised of a Novolac resin and a diazonaphthoquinone photoactive compound is coated on a substrate and baked at or slightly above its Tg so that it reflows and fills the holes. The photoresist is exposed without a mask at a dose that allows the developer to thin the photoresist to a recessed depth within the holes. After the photoresist is hardened with a 250° C. bake, a second photoresist is coated on the substrate to form a planarized film with a thickness variation of less than 50 Angstroms between low and high duty ratio hole regions. One application is where the second photoresist is used to form a trench pattern in a via first dual damascene method. Secondly, the method is useful in fabricating MIM capacitors.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: November 11, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chia-Tung Ho, Feng-Jia Shih, Jieh-Jang Chen, Ching-Sen Kuo, Shih-Chi Fu, Gwo-Yuh Shiau, Chia-Shiung Tsia