Abstract: A semiconductor device includes a substrate and two fins protruding from the substrate. Each fin includes two source/drain (S/D) regions and a channel region. Each fin includes a top surface that remains flat across the S/D regions and the channel region. The semiconductor device also includes a gate stack engaging each fin at the respective channel region, a first dielectric layer on sidewalls of the gate stack, a first epitaxial layer over top and sidewall surfaces of the S/D regions of the two fins, and a second epitaxial layer over top and sidewall surfaces of the first epitaxial layer.

Abstract: A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

Abstract: A memory device includes a three dimensional memory array having memory cells arranged on multiple floors in rows and columns. Each column is associated with a bit line and a select line. The memory device further includes select gate pairs each being associated with a column. The bit line of a column is connectable to a corresponding a global bit line through a first select gate of a select gate pair associated with the column and a select line of the column is connectable to a corresponding global select line through the second select gate of the select gate pair associated with the column. The plurality of select gate pairs are formed in a different layer than the plurality of memory cells.

Abstract: Embodiments of the present disclosure provide a side-channel dynamic random access memory (DRAM) cell and cell array that utilizes a vertical design with side channel transistors. A dielectric layer disposed over a substrate. A gate electrode is embedded in the dielectric layer. A channel layer wraps the gate electrode and a conductive structure is adjacent to the channel layer, with the channel layer interposed between the gate electrode and the conductive structure. The semiconductor structure also includes a dielectric structure disposed over the conductive structure and the gate electrode, the channel layer extending up through the dielectric structure.

Abstract: A semiconductor structure includes fins protruding from a substrate and separated by a dielectric layer, each semiconductor fin including a plurality of semiconductor layers, source/drain (S/D) features disposed in the semiconductor fins, a first metal gate stack and a second metal gate stack disposed over the semiconductor fins and adjacent to the S/D features, where the first and the second metal gate stacks each include a top portion and a bottom portion disposed below the top portion, and where the bottom portion is interleaved with the semiconductor layers, and an isolation feature disposed on the dielectric layer and in contact with a sidewall surface of each of the first and the second metal gate stacks, where the isolation feature protrudes from the top portion of the first and the second metal gate stack, and where the isolation feature includes two compositionally different dielectric layers.

Abstract: A memory device includes a three dimensional memory array having memory cells arranged on multiple floors in rows and columns. Each column is associated with a bit line and a select line. The memory device further includes select gate pairs each being associated with a column. The bit line of a column is connectable to a corresponding a global bit line through a first select gate of a select gate pair associated with the column and a select line of the column is connectable to a corresponding global select line through the second select gate of the select gate pair associated with the column. The plurality of select gate pairs are formed in a different layer than the plurality of memory cells.

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

Abstract: One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

Abstract: A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

Abstract: The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers.

Abstract: One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.

Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Abstract: The present disclosure is directed to methods for the fabrication of buried layers in gate-all-around (GAA) transistor structures to suppress junction leakage. In some embodiments, the method includes forming a doped epitaxial layer on a substrate, forming a stack of alternating first and second nano-sheet layers on the epitaxial layer, and patterning the stack and the epitaxial layer to form a fin structure. The method includes forming a sacrificial gate structure on the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, and etching portions of the first nano-sheet layers. Additionally, the method includes forming spacer structures on the etched portions of the first nano-sheet layers and forming source/drain (S/D) epitaxial structures on the epitaxial layer abutting the second nano-sheet layers.

Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

Abstract: Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a gate electrode disposed in an insulating material layer, a ferroelectric dielectric layer disposed over the gate electrode, a metal oxide semiconductor layer disposed over the ferroelectric dielectric layer, a source feature disposed over the metal oxide semiconductor layer, wherein the source feature has a first dimension, and a source extension. The source extension includes a first portion disposed over the source feature, wherein the first portion has a second dimension that is greater than the first dimension. The source extension also includes a second portion extending downwardly from the first portion to an elevation that is lower than a top surface of the source feature.

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Abstract: A semiconductor structure includes a first fin and a second fin protruding from a substrate, isolation features over the substrate to separate the first and the second fins, where a top surface of each of the first and the second fins is below a top surface of the isolation features, inner fin spacers disposed along inner sidewalls of the first and the second fins, where the inner fin spacers have a first height measured from a top surface of the isolation features, outer fin spacers disposed along outer sidewalls of the first and the second fins, where the outer fin spacers have a second height measured from the top surface of the isolation features that is less than the first height, and a source/drain (S/D) structure merging the first and the second fins, where the S/D structure includes an air gap having a top portion over the inner fin spacers.