Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: A pin set is provided for a reactor, and the pin set has a lift pin, a pin guide and a pin weight. The pin guide is configured in the reactor and has a guide hole for the lift pin to move through. A guide gap is positioned between the guide hole and the lift pin. The pin weight has a weight hole, and a first end of the lift pin passes through the weight hole and is fixed on the pin weight. A weight gap is positioned between the weight hole and the lift pin, and the weight gap is smaller than the guide gap.

Abstract: An EEPROM integrated circuit structure. The structure has a substrate that includes a surface region. Preferably, the surface region is provided within a first cell region. The structure also has a gate dielectric layer of first thickness overlying the surface of the substrate region and a select gate overlying a first portion of the gate dielectric layer. A floating gate is overlying a second portion of the gate dielectric layer and is coupled to the select gate. An insulating layer is overlying the floating gate. A control gate is overlying the insulating layer and is coupled to the floating gate. A tunnel window provided in a stripe configuration is formed within a portion of the gate dielectric layer. The portion of the gate dielectric layer is characterized by a second thickness, which is less than the first thickness.

Abstract: A method for fabricating a non-volatile memory on the semiconductor substrate is disclosed. First of all, a plurality of trench isolation regions are formed. Then, firstly implanting ions of a first conductivity type and second conductivity type are carried out. Secondly implanting ions of the first conductivity type and second conductivity type are carried out. Then, a first oxide layer is deposited and the first oxide layer is removed. A second oxide layer is deposited. A portion of second oxide is removed, thus, a portion of second oxide layer is remained. A third oxide layer is formed. A first polysilicon layer is formed. The first polysilicon layer is etched. A oxide-nitride-oxide layer is formed. Consequentially, the oxide-nitride-oxide layer are all etched. The second polysilicon on is formed. A portion of the second polysilicon layer, a portion of the first polysilicon layer, a portion of the third oxide layer and a portion of the second oxide layer are all etched. Thus, capacitor columns are formed.