Patents by Inventor Chia-Tien Chou

Chia-Tien Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916077
    Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Ru-Gun Liu, Wei-Cheng Lin, Lei-Chun Chou, Wei-An Lai
  • Patent number: 10483334
    Abstract: A display panel comprising a first substrate, a second substrate, a color conversion layer, and an image sensing layer. A plurality of display units are between the first substrate and the second substrate. At least one of the plurality of display units has at least three sub-pixels. Each of the sub-pixels at least has one display region and a light shielding region disposed on at least one side of the display region. The color conversion layer is disposed in the display unit. Each of the color conversion elements is disposed in at least one portion of the light shielding region of each of the sub-pixels. The image sensing layer is disposed on the display unit and at least partially overlaps the color conversion layer. Each of the image sensing elements is disposed in at least one portion of the light shielding region of each of the sub-pixels to serve as an image sensing region.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: November 19, 2019
    Assignee: Au Optronics Corporation
    Inventors: Yu-Chin Wu, Chia-Tien Chou
  • Publication number: 20190348480
    Abstract: A display panel comprising a first substrate, a second substrate, a color conversion layer, and an image sensing layer. A plurality of display units are between the first substrate and the second substrate. At least one of the plurality of display units has at least three sub-pixels. Each of the sub-pixels at least has one display region and a light shielding region disposed on at least one side of the display region. The color conversion layer is disposed in the display unit. Each of the color conversion elements is disposed in at least one portion of the light shielding region of each of the sub-pixels. The image sensing layer is disposed on the display unit and at least partially overlaps the color conversion layer. Each of the image sensing elements is disposed in at least one portion of the light shielding region of each of the sub-pixels to serve as an image sensing region.
    Type: Application
    Filed: July 18, 2018
    Publication date: November 14, 2019
    Applicant: Au Optronics Corporation
    Inventors: Yu-Chin Wu, Chia-Tien Chou
  • Patent number: 10170714
    Abstract: A display panel includes a first substrate, an upper capacitor electrode, a capacitor dielectric layer, a second substrate opposite to the first substrate, a conductive bump, an electroluminescent layer, and a counter electrode. The upper capacitor electrode is disposed on an inner surface of the second substrate. The upper capacitor electrode is disposed on an inner surface of the second substrate. The capacitor dielectric layer covers the upper capacitor electrode of the second substrate. The first substrate has at least one pixel electrode and a first capacitor electrode separated from the pixel electrode. The conductive bump is protrusively disposed on the first capacitor electrode of the first substrate. The electroluminescent layer is sandwiched between the pixel electrode and the counter electrode.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: January 1, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chia-Tien Chou, Ya-Chun Chang
  • Patent number: 10062859
    Abstract: A display panel includes a substrate, a conductive bump, a capacitor dielectric layer, a sensing electrode, a counter substrate opposite to the substrate, an electroluminescent layer, and a counter electrode. The conductive bump protrudes from an inner surface of the substrate and includes an upper capacitor electrode and a bump covered by the upper capacitor electrode. The bump is disposed between the inner surface of the substrate and the upper capacitor electrode. The capacitor dielectric layer covers the conductive bump and a portion of the inner surface of the substrate. The sensing electrode is disposed on the inner surface of the substrate or an inner surface of the counter substrate. The counter substrate has at least one pixel electrode and a first capacitor electrode separated from the pixel electrode. The electroluminescent layer is disposed between the pixel electrode and the counter electrode.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: August 28, 2018
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chia-Tien Chou, Ya-Chun Chang
  • Publication number: 20180013081
    Abstract: A display panel includes a first substrate, an upper capacitor electrode, a capacitor dielectric layer, a second substrate opposite to the first substrate, a conductive bump, an electroluminescent layer, and a counter electrode. The upper capacitor electrode is disposed on an inner surface of the second substrate. The upper capacitor electrode is disposed on an inner surface of the second substrate. The capacitor dielectric layer covers the upper capacitor electrode of the second substrate. The first substrate has at least one pixel electrode and a first capacitor electrode separated from the pixel electrode. The conductive bump is protrusively disposed on the first capacitor electrode of the first substrate. The electroluminescent layer is sandwiched between the pixel electrode and the counter electrode.
    Type: Application
    Filed: July 10, 2017
    Publication date: January 11, 2018
    Inventors: Chia-Tien CHOU, Ya-Chun CHANG
  • Publication number: 20180013086
    Abstract: A display panel includes a substrate, a conductive bump, a capacitor dielectric layer, a sensing electrode, a counter substrate opposite to the substrate, an electroluminescent layer, and a counter electrode. The conductive bump protrudes from an inner surface of the substrate and includes an upper capacitor electrode and a bump covered by the upper capacitor electrode. The bump is disposed between the inner surface of the substrate and the upper capacitor electrode. The capacitor dielectric layer covers the conductive bump and a portion of the inner surface of the substrate. The sensing electrode is disposed on the inner surface of the substrate or an inner surface of the counter substrate. The counter substrate has at least one pixel electrode and a first capacitor electrode separated from the pixel electrode. The electroluminescent layer is disposed between the pixel electrode and the counter electrode.
    Type: Application
    Filed: July 6, 2017
    Publication date: January 11, 2018
    Inventors: Chia-Tien CHOU, Ya-Chun CHANG
  • Patent number: 5553323
    Abstract: An upper garment for patients which includes a back panel for covering over the back of a patient, two front panels sewed up with the back panel and fastened together by a zipper and respectively fastened to either side of the back panel by a respective zipper for covering over the front side of the upper body of the patient, two opposite sleeve panels respectively sewn up with the back panel and fastened up into a sleeve by a respective zipper in the longitudinal direction for covering around the hands of the patient.
    Type: Grant
    Filed: July 11, 1994
    Date of Patent: September 10, 1996
    Inventors: Chia-Tien Chou, Chao-Mu Chao
  • Patent number: 5392466
    Abstract: An upper garment including a garment body formed by connecting a front half body panel with a back half body panel, and two sleeves respectively formed by connecting a respective front half sleeve panel with a respective back half sleeve panel, the front half body panel having at least one side detachably connected to a corresponding side of the back half body panel, the front half sleeve panel of at least one sleeve has one side detachably connected to a corresponding side of the respective back sleeve panel. An armpit hole, a shoulder hole, and a pocket with a through hole are respectively made on the garment body and shielded with a respective flap.
    Type: Grant
    Filed: April 29, 1993
    Date of Patent: February 28, 1995
    Inventors: Chia-Tien Chou, Chao-Mu Chou