Abstract: An integrated circuit includes conductive rails that are disposed in a first conductive layer and separated from each other in a layout view, signal rails disposed in a second conductive layer different from the first conductive layer, at least one first via coupling a first signal rail of the signal rails to at least one of the conductive rails, and at least one first conductive segment. The first signal rail transmits a supply signal through the at least one first via and the at least one of the conductive rails to at least one element of the integrated circuit. The at least one first via and the at least one first conductive segment are disposed above first conductive layer. The at least one first conductive segment is coupled to the at least one of the conductive rails and is separate from the first signal rail.

Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.

Abstract: An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer disposed over a substrate, a second dielectric layer disposed over the first dielectric layer, and a first conductive feature disposed in the second dielectric layer. The first conductive feature has a first top critical dimension and a first height. The structure further includes a second conductive feature disposed in the first and second dielectric layers. The second conductive feature has a second top critical dimension substantially greater than the first top critical dimension and a second height substantially greater than the first height.

Abstract: An integrated circuit includes a plurality of first layer deep lines, a plurality of first layer shallow lines, a plurality of second layer deep lines, and a plurality of second layer shallow lines. The integrated circuit also includes a first active device and a second active device coupled between a conducting path that has a low resistivity portion and a low capacitivity portion. The first active device has an output coupled to a first layer deep line that is in the low resistivity portion. The second active device has an input coupled to a first layer shallow line that is in the low capacitivity portion. The low resistivity portion excludes the first layer shallow lines and the second layer shallow lines, and the low capacitivity portion excludes the first layer deep lines and the second layer deep lines.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: A connecting structure includes a first dielectric layer, a first connecting via in the first dielectric layer, a second connecting via in the first dielectric layer, and an isolation between the first connecting via and the second connecting via. The isolation separates the first and second connecting vias from each other. The first connecting via, the isolation and the second connecting via are line symmetrical about a central line perpendicular to a top surface of the first dielectric layer.

Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy structures spaced apart from each other, forming a plurality of dielectric spacers laterally covering the dummy structures to form a plurality of trenches defined by the dielectric spacers, filling a conductive material into the trenches to form electrically conductive features, selectively depositing a capping material on the electrically conductive features to form a capping layer, removing the dummy structures to form a plurality of recesses defined by the dielectric spacers, filling a sacrificial material into the recesses so as to form sacrificial features, depositing a sustaining layer on the sacrificial features, and removing the sacrificial features to form air gaps confined by the sustaining layer and the dielectric spacers.

Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of first metal strips extending in a first direction on a first plane; and forming a plurality of second metal strips extending in the first direction on a second plane over the first plane by executing a photolithography operation with a single mask, wherein a first second metal strip (FIG. 1, 131) is disposed over a first first metal strip; wherein the first first metal strip and the first second metal strip are directed to a first voltage source; wherein a distance between the first second metal strip and a second second metal strip immediate adjacent to the first second metal strip is greater than a distance between the second second metal strip and a third second metal strip immediate adjacent to the second second metal strip.

Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: An integrated circuit includes a plurality of horizontal conducting lines in a first connection layer, a plurality of gate-conductors below the first connection layer, a plurality of terminal-conductors below the first connection layer, and a via-connector directly connecting one of the horizontal conducting lines with one of the gate-conductors or with one of the terminal-conductors. The integrated circuit also includes a plurality of vertical conducting lines in a second connection layer above the first connection layer, and a plurality of pin-connectors for a circuit cell. A first pin-connector is directly connected between a first horizontal conducting line and a first vertical conducting line atop one of the gate-conductors. A second pin-connector is directly connected between a second horizontal conducting line and a second vertical conducting line atop a vertical boundary of the circuit cell.

Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Abstract: An integrated circuit includes a first conductive structure including a root portion of the first conductive structure, tine portions that are arranged in a first semiconductor layer, a neck portion surrounded by a film structure. The integrated circuit further includes a second conductive structure having first and second portions that are stacked along a first direction. The first portion of the second conductive structure is surrounded by the film structure and the second portion of the second conductive structure is in the first semiconductor layer. A third conductive structure in the integrated circuit has horizontal and vertical structures. The horizontal structure extends in a second semiconductor layer and the vertical structure passes through the second semiconductor layer and the film structure to contact a first conductive rail. The first conductive rail and the tine portions are apart from the horizontal structure along the first direction by a same distance.

Abstract: A semiconductor device includes first and second conductive layers, a first epitaxial structure and a first via structure. The first conductive layer extends along a first direction, and provides a first reference voltage signal. The second conductive layer extends along the first direction, and is separated from the first conductive layer along a second direction. The first epitaxial structure is disposed between the first conductive layer and the second conductive layer, and has a first width along the first direction. The first via structure is disposed between the first conductive layer and the second conductive layer, and transmits the first reference voltage signal from the first conductive layer through the second conductive layer to the first epitaxial structure. The first via structure has a second width along the first direction. The second width is approximately equal to or larger than twice of the first width.

Abstract: An integrated circuit includes a plurality of first layer deep lines and a plurality of first layer shallow lines. The integrated circuit also includes a plurality of second layer deep lines and a plurality of second layer shallow lines. Each of the first layer deep lines and the first layer shallow lines is in a first conductive layer. Each of the second layer deep lines and the second layer shallow lines is in a second conductive layer above the first conductive layer.

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, an isolation layer, a first electronic device, a first interconnection structure, a first conductive structure, and a second conductive structure. The substrate has a first surface and a second surface opposite the first surface. The isolation layer contacts the second surface of the substrate and has a first surface facing away from the substrate. The first electronic device is embedded in the substrate. The first interconnection structure extends from the first surface of the substrate to the first surface of the isolation layer. The first conductive structure is disposed on the first surface of the substrate. The second conductive structure contacts the first surface of the isolation layer. The first conductive structure and the second conductive structure are electrically connected by the first interconnection structure.

Abstract: A method includes fabricating semiconductor structures extending in a first direction and fabricating gate-conductors extending in a second direction intersecting the semiconductor structure. The method also includes patterning a first metal layer to form horizontal conducting lines extending in the first direction, and patterning the second metal layer to form vertical conducting lines extending in the second direction. A first vertical conducting line is aligned with a first gate-conductor underneath and a second vertical conducting line is aligned with a vertical boundary of a circuit cell. The first vertical conducting line is directly connected to a first horizontal conducting line through a first pin-connector, and the second vertical conducting line is directly connected to a second horizontal conducting line through a second pin-connector.

Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

Abstract: The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.

Abstract: A semiconductor device includes a substrate, an interconnect layer disposed over the substrate and including a metal line, and a dielectric layer disposed on the interconnect layer and including a via contact. The via contact is electrically connected to the metal line and has a first dimension in a first direction greater than a second dimension in a second direction. The first direction and the second direction are perpendicular to each other, and are both perpendicular to a longitudinal direction of the via contact.