Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

Abstract: The present disclosure provides a method for forming an interconnect structure, including forming an Nth metal line principally extending in a first direction, forming a sacrificial bilayer over the Nth metal line, forming a dielectric layer over the sacrificial bilayer, removing a portion of the sacrificial bilayer, forming a conductive post in the sacrificial bilayer, wherein the conductive post having a top pattern coplanar with a top surface of the sacrificial bilayer and a bottom pattern in contact with a top surface of the Nth metal line, and forming an Nth metal via over the sacrificial bilayer.

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

Abstract: An interconnection structure includes a first dielectric layer, a conductive element, a second dielectric layer, a bottom via, a dielectric spacer, and a top via. The conductive element is embedded in the first dielectric layer. The second dielectric layer is over the first dielectric layer and the conductive element. The second dielectric layer has an opening exposing the conductive element. The bottom via is disposed in the opening and in contact with the conductive element. The dielectric spacer is disposed in the opening and is in contact with the bottom via and the second dielectric layer. The top via is disposed in the opening and covering the bottom via and the dielectric spacer.

Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.

Abstract: A method for patterning a metal layer includes depositing a hard mask layer on a metal layer, depositing a first patterned layer on the hard mask layer, forming a first set of sidewall spacers on sidewalls of features of the first patterned layer, forming a second set of sidewall spacers on sidewalls of the first set of sidewall spacers, removing the first set of sidewall spacers, and performing a reactive ion etching process to pattern portions of the metal layer exposed through the first patterned layer and the second set of sidewall spacers.

Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.

Abstract: The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.

Abstract: The present disclosure provides a method for forming an interconnect structure, including forming an Nth metal line principally extending in a first direction, forming a sacrificial bilayer over the Nth metal line, forming a dielectric layer over the sacrificial bilayer, removing a portion of the sacrificial bilayer, forming a conductive post in the sacrificial bilayer, wherein the conductive post having a top pattern coplanar with a top surface of the sacrificial bilayer and a bottom pattern in contact with a top surface of the Nth metal line, and forming an Nth metal via over the sacrificial bilayer.

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

Abstract: A semiconductor structure includes a first dielectric layer; a first conductive member extended through and surrounded by the first dielectric layer; a first protective layer disposed over the first dielectric layer and the first conductive member; a second dielectric layer disposed over the first protective layer; a third dielectric layer disposed over the second dielectric layer; and a second conductive member disposed over the first dielectric layer and the first conductive member, and surrounded by the first protective layer, the second dielectric layer and the third dielectric layer, wherein the second conductive member includes a first portion and a second portion disposed over and coupled with the first portion, the first portion is extended through and surrounded by the first protective layer and the second dielectric layer, the second portion is surrounded by the third dielectric layer.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a first dielectric layer over a semiconductor substrate and forming a first conductive feature extending into the first dielectric layer. The first conductive feature has a planar top surface. The method also includes forming a second dielectric layer over the first conductive feature. The method further includes forming a hole in the second dielectric layer to expose the planar top surface of the first conductive feature. In addition, the method includes partially removing the first conductive feature from the planar top surface of the first conductive feature to form a curved surface of the first conductive feature. The method further includes forming a second conductive feature to fill the hole after the curved surface of the first conductive feature is formed.

Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first conductive feature in a first dielectric layer and a second conductive feature over the first dielectric layer. The semiconductor device structure also includes a conductive via between the first conductive feature and the second conductive feature. The conductive via includes an etching stop layer over the first conductive feature, a conductive pillar over the etching stop layer, and a capping layer surrounding the conductive pillar and the etching stop layer. The first conductive feature and the second conductive feature are electrically connected to each other through the capping layer, the conductive pillar, and the etching stop layer. The semiconductor device structure further includes a second dielectric layer over the first dielectric layer and below the second conductive feature. The second dielectric layer surrounds the conductive via.

Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.

Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.

Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The semiconductor device also includes a first dielectric layer over the semiconductor substrate and surrounding the first conductive feature. The semiconductor device further includes a second conductive feature over the first conductive feature. A bottom surface of the second conductive feature is between a top surface of the first conductive feature and a bottom surface of the first conductive feature. In addition, the semiconductor device includes a second dielectric layer over the first dielectric layer and surrounding the second conductive feature. The semiconductor device also includes an etch stop layer between the first dielectric layer and the second dielectric layer. A top surface of the etch stop layer is between the top surface and the bottom surface of the first conductive feature.

Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.

Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.