Abstract: A chemical compound including Isopropyl-D-glucopyranoside derivatives and its chemical synthesis to prepare the chemical compound. The Isopropyl-D-glucopyranoside derivatives is used for promoting regeneration of injured brain neurons and retinal neurons.

Abstract: An image processing device and an image processing method of generating a layout including a plurality of images are provided. The method includes: partitioning the layout into a plurality of tiles; selecting a first tile located at a border of a first display region and a second display region, and cropping a first sub-block from the first tile; mapping the first sub-block to a calibration map to obtain a mapping region; in response to a third vertex in the mapping region corresponding to a first vertex and a second vertex, performing an interpolation operation on a first data structure and a second data structure to obtain a third data structure corresponding to the third vertex; generating a composed vertex list according to the third vertex and the third data structure; and generating an output image by mapping an input image to the layout according to the composed vertex list.

Abstract: A semiconductor device and a manufacturing method thereof are in the present invention. The semiconductor device includes a substrate, a source structure, a semiconductor structure, a gate structure, a barrier pattern. The source structure is disposed on the substrate, the semiconductor structure is disposed above the source structure in a vertical direction, and the gate structure is disposed above the source structure and surrounds the semiconductor structure in a horizontal direction. The barrier pattern is disposed between the gate structure and the semiconductor structure in the horizontal direction. The gate structure surrounds the barrier pattern in the horizontal direction, and the barrier pattern surrounds the semiconductor structure in the horizontal direction. Accordingly, the operation performance of the semiconductor device may be improved.

Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.

Abstract: An apparatus may include a display stack, an ultrasonic sensor stack and a high-impedance stack including one or more high-impedance layers. The ultrasonic sensor stack may include an ultrasonic transceiver layer and an ultrasonic transceiver circuitry (UTC) layer. Each of the high-impedance layers may have an acoustic impedance that is higher than an acoustic impedance of the UTC layer. The high-impedance stack and the ultrasonic sensor stack may form an acoustic resonator bounded by the UTC layer and the high-impedance stack. The acoustic resonator may be configured to enhance the ultrasonic waves transmitted by the ultrasonic sensor stack at a peak frequency of the ultrasonic sensor stack. The peak frequency may be a frequency used by the ultrasonic sensor stack for obtaining fingerprint images. An apparatus stack portion that includes the ultrasonic sensor stack may have a thickness corresponding to a multiple of a quarter wavelength at the peak frequency.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a drain contact on opposing sides of the epitaxial layer of the source contact, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, and wherein the breakdown voltage enhancement and leakage prevention structure comprises a reduced surface field (RESURF) structure.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

Abstract: A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer, comprising a reduced surface field (RESURF) structure, forming a source in the epitaxial layer and a gate-source Electrostatic Discharge (ESD) diode structure over the epitaxial layer, forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, and forming a drain contact on the opposing side of the epitaxial layer from the source contact.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

Abstract: An integrated liquid-cooled temperature equalization module includes a top cover and a temperature equalization plate. The top cover includes a first flow channel, a second flow channel, a passage connecting the first and second flow channels, an inlet connecting the first flow channel for coolant flowing into the top cover, and an outlet connecting the second flow channel for coolant flowing out of the top cover. The temperature equalization plate includes a main body having a cooling zone, a tin soldering surface, and a protrusion; a first heat sink unit mounted on the cooling zone and accommodated in the first flow channel; a second heat sink unit mounted on the cooling zone and accommodated in the second flow channel; and an internal support structure accommodated in the protrusion. Accordingly, heat dissipation efficiency of the present disclosure is improved and made more uniform.

Abstract: A method for adjusting compression rate is provided. The method includes compressing data at a compression rate and storing the data into a memory using a processing circuit. The method further includes calculating a compression rate adjustment parameter based on each time duration for reading or writing the memory in a first specific period of time and a time threshold using the processing circuit. The method further includes adjusting the compression rate based on the compression rate adjustment parameter using a processing circuit.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

Abstract: A cooling motor includes a motor device having a motor casing, a motor assembly arranged in the motor casing, and a centrifugal fan, and a cooling device having first and second cooling components. The first cooling component includes a first cold plate jacket and a first heat circulation pipeline. The first cold plate jacket is sleeved on the motor assembly and thermally connected to a stator, and the first cold plate jacket includes first cold plates. The first thermal circulation pipeline filled with a first working fluid passes through the first cold plate jacket. The second cooling component includes a second cold plate jacket and a second heat circulation pipeline. The second cold plate jacket, sleeving the first cold plate jacket in an insulation manner, includes second cold plates and cooling fins. The second thermal circulation pipeline filled with a second working fluid passes through the second cold plate jacket.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

Abstract: A heat dissipation assembly is provided. The heat dissipation assembly includes a heat source, an upper cover, and a heat dissipation device. The upper cover includes a first upper cover surface and a second upper cover surface. The first upper cover surface receives the thermal energy from the heat source. The heat dissipation device is located under the upper cover and adjacent to the second upper cover surface to cool the second upper cover surface. The upper cover is a thermoelectric generator chip.

Abstract: A semiconductor device structure and method that utilizes anti-reflection components. The structure includes at least one ramp VIA formed in a VIA isolator layer, at least one anti-reflection component formed on the at least one ramp VIA. A trench isolator layer is formed on the at least one anti-reflection component, and a photoresist is selectively patterned on the trench isolator layer. The trench isolator layer and a portion of the at least one anti-reflection component is etched based upon the selectively patterned photoresist to form a trench metal component hole above the at least one ramp VIA. Thereafter, a trench metal component is formed in the trench metal component hole.

Abstract: Provided are methods and compositions for obtaining functionally enhanced derivative effector cells obtained from directed differentiation of genomically engineered iPSCs. Also provided are derivative cells having stable and functional genome editing that delivers improved or enhanced therapeutic effects. Further provided are therapeutic compositions and the use thereof comprising the functionally enhanced derivative effector cells alone, or with antibodies or checkpoint inhibitors in combination therapies.

Abstract: An integrated circuit device and a method of manufacturing the same are provided. The method includes steps of: forming a semiconductor device on a substrate; forming a first interconnect structure and a dielectric layer over the semiconductor device; and forming a second interconnect structure over the first interconnect structure, wherein the formation of the second interconnect structure includes: forming an insulating film over the first interconnect structure; depositing an etch stop layer over the insulating film, wherein the etch stop layer and the insulating film include different materials; depositing an isolation layer over the etch stop layer; performing a first etching operation to form a via penetrating the isolation layer and exposing the etch stop layer; and performing a second etching operation to extend the via downward to penetrate the etch stop layer and the insulating film and expose a portion of the first interconnect structure.