Abstract: Methods, machine readable media and systems for evaluating, through one or more simulations, the leakage of sensitive data in an integrated circuit, such as cryptographic data or keys, are described. The embodiments can use machine learning models, such as one or more neural networks to generate one or more leakage related scores for each portion in a set of portions of the cryptographic data. In one embodiment, leakage data associated the first set of POIs with one or more neural networks is processed by the one or more neural networks to identify the POIs that leak the most and determine one or more scores for each portion in the set of portions of the cryptographic data.

Abstract: An apparatus includes a motor having one or more gears and a shaft operably coupled to the one or more gears. The shaft actuates to adjust a field of view (FoV) of a camera. The apparatus further includes a bracket having a passage in which the shaft is at least partially disposed, and a channel. A spring is at least partially disposed with the channel of the bracket and is configured to reduce a backlash within the one or more gears of the motor.

Abstract: A method includes forming a fin protruding from a semiconductor substrate, forming source/drain features in the fin, forming a metal gate structure over the fin and interposed between the source/drain features, recessing the metal gate structure to form a trench, depositing a first metal layer to partially fill the trench, depositing a second metal layer to completely fill the trench, and planarizing the second meal layer. The second metal layer differs from the first metal layer in composition, and the second metal layer includes tungsten (W).

Abstract: In a method of manufacturing a semiconductor device, a lower conductive layer is formed in an opening formed in a dielectric layer, and the lower conductive layer is recessed to form a space. A blanket conductive layer is formed over the recessed lower conductive layer in the space, a sidewall of the space and an upper surface of the dielectric layer. Part of the blanket conductive layer formed on the sidewall of the space and the upper surface of the dielectric layer is removed, thereby forming an upper conductive layer on the lower conductive layer, and a cap insulating layer is formed over the upper conductive layer in the space. The blanket conductive layer is formed by physical vapor deposition.

Abstract: A semiconductor device includes a substrate, a channel layer over the substrate, a gate structure over the channel layer, a source electrode and a drain electrode on opposite sides of the gate structure and electrically connected with the channel layer, and a field plate between the gate structure and the drain electrode. The field plate vertically overlaps an edge of the gate structure.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.

Abstract: Disclosed are cooling systems and methods for detecting coolant leakage. Processors of servers are attached to cold plates. An internal liquid coolant is contained in a coolant reservoir and is circulated through the cold plates via a coolant distribution manifold. The level of the internal liquid coolant is monitored in the coolant distribution manifold and the coolant reservoir. Coolant leakage is detected based at least on the level of the internal liquid coolant in the coolant distribution manifold and detection of internal coolant leakage in the servers.

Abstract: Disclosed is a cooling assembly for processors and voltage regulators. A processor is attached to a cold plate. A voltage regulator heatsink is removably attached to the cold plate. The voltage regulator heatsink has cooling fins and a heatsink base. The heatsink base is attached to a voltage regulator. Liquid coolant is flowed through the cold plate to cool the processor and the voltage regulator.

Abstract: This application is directed to heat dissipation for a server system. A server rack includes a rack structure including a plurality of slots for receiving at least one or more rack servers. The server rack includes a first coolant distribution manifold coupled to a first front edge of the rack structure that extends adjacent to the plurality of slots. The first coolant distribution manifold includes a plurality of outlets configured to provide coolant flows to the one or more rack servers from the first front edge of the rack structure. The server rack further includes a second coolant distribution manifold coupled to a second front edge of the rack structure that extends adjacent to the plurality of slots. The second coolant distribution manifold includes a plurality of inlets configured to collect, from the second front edge of the rack structure, the coolant flows exiting the one or more rack servers.

Abstract: A system for providing power to a system load is disclosed. The system may comprise a power supply unit (PSU). A controller configured to receive data from the PSU and an input switch connected to the PSU may also be included. The system may also comprise an input capacitor connected to the input switch, an output capacitor connected to the input capacitor, and an output switch connected to a system load. The system may be configured to provide boost power to the system load when a constant current mode is determined.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, an n-type work function layer embedded in the gate dielectric layer, a dielectric capping layer embedded in the n-type work function layer, and a p-type work function layer embedded in the dielectric capping layer. A top surface of the gate structure exposes the n-type work function layer, the dielectric capping layer, and the p-type work function layer. The semiconductor structure also includes a first metal cap on the n-type work function layer and a second metal cap on the p-type work function layer. The first metal cap is spaced apart from the second metal cap. without formed on the dielectric capping layer.

Abstract: Ruthenium of a metal gate (MG) and/or a middle end of line (MEOL) structure is annealed to reduce, or even eliminate, seams after the ruthenium is deposited. Because the annealing reduces (or removes) seams in deposited ruthenium, electrical performance is increased because resistivity of the MG and/or the MEOL structure is decreased. Additionally, for MGs, the annealing generates a more even deposition profile, which results in a timed etching process producing a uniform gate height. As a result, more of the MGs will be functional after etching, which increases yield during production of the electronic device.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a channel structure and an epitaxial structure beside the channel structure. The semiconductor device structure also includes a metal gate stack over the semiconductor nanostructures. The metal gate stack includes a gate dielectric layer, a first work function layer over the gate dielectric layer, and a metal oxide layer over the first work function layer. The metal oxide layer is thinner than the first work function layer. The metal gate stack also includes a second work function layer over the metal oxide layer.

Abstract: Ruthenium of a metal gate (MG) and/or a middle end of line (MEOL) structure is annealed to reduce, or even eliminate, seams after the ruthenium is deposited. Because the annealing reduces (or removes) seams in deposited ruthenium, electrical performance is increased because resistivity of the MG and/or the MEOL structure is decreased. Additionally, for MGs, the annealing generates a more even deposition profile, which results in a timed etching process producing a uniform gate height. As a result, more of the MGs will be functional after etching, which increases yield during production of the electronic device.

Abstract: A driving assistance system and a driving assistance method are provided. The driving assistance system includes a plurality of image capturing devices, a congestion calculation module, and a determination module. The image capturing devices capture a plurality of regional images of a plurality of road sections of the target lane. The congestion calculation module calculates a plurality of congestion levels corresponding to the road sections according to the regional images. The determination module provides a lane changing message to the vehicle according to the congestion levels.

Abstract: A semiconductor device structure includes first nanostructures and second nanostructures over a substrate. The semiconductor device structure also includes a first metal gate layer surrounding the first nanostructures. The semiconductor device structure further includes a second metal gate layer surrounding the second nanostructures and over the first metal gate layer. The first metal gate layer comprises N-work-function metal, and the second metal gate layer comprises P-work-function metal.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes removing the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor lavers. The method further includes forming a gate dielectric layer to wrap around the semiconductor nanostructures and forming a first metal-containing layer over the gate dielectric layer to wrap around the semiconductor nanostructures. In addition, the method includes introducing oxygen-containing plasma on the first metal-containing layer to transform an upper portion of the first metal-containing layer into a metal oxide layer. The method includes forming a second metal-containing layer over the metal oxide layer.

Abstract: A method for forming a semiconductor device structure includes forming first nanostructures and second nanostructures over a substrate. The method also includes forming a first metal gate layer surrounding the first nanostructures and over the first nanostructures and the second nanostructures. The method also includes etching back the first metal gate layer over the first nanostructures and the second nanostructures. The method also includes removing the first metal gate layer over the second nanostructures. The method also includes forming a second metal gate layer surrounding the second nanostructures and over the first nanostructures and the second nanostructures.

Abstract: A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.