Patents by Inventor Chia-Wei Chiang

Chia-Wei Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240125771
    Abstract: The present invention relates to a reaction platform, which comprises: a machine body with a bottom plate for placing non-porous substrates; and a coater module configured on the top of the machine body and capable of maintaining a preset of a predetermined height for moving along the surface of non-porous substrate, wherein the coater module has one or more slits, and a target liquid can be directly injected or sucking in from the outside of the coater module through the slit, and spreading the target liquid onto a surface of the non-porous substrate while moving along the non-porous substrate; wherein the surface of the non-porous substrate has a target to be coated. The reaction platform of the present invention can not only save time, labor and cost, but also have accurate and reproducible experimental results, showing better results than traditional methods.
    Type: Application
    Filed: July 25, 2023
    Publication date: April 18, 2024
    Inventors: An-Bang Wang, Shih-Yu Chen, Tung-Hung Su, Chia-Chi Chu, Chia-Chien Yen, Yu-Wei Chiang
  • Publication number: 20240123463
    Abstract: An atomization module includes a main fixing member, an auxiliary fixing member, an atomization component and a piezoelectric component. The main fixing member includes a first bonding part, a second bonding part and a connecting part. The first bonding part has a first opening and a first bonding surface surrounding the first opening. The second bonding part is connected to the first bonding part, and the connecting part and the second bonding part surround the first bonding part. The auxiliary fixing member has a second opening and a second bonding surface surrounding the second opening. The piezoelectric component surrounds the first bonding part. The main fixing member has a first adhesive groove, which is jointly defined at least by the main fixing member, the auxiliary fixing member and the atomization component. The first adhesive is provided in the first adhesive groove.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 18, 2024
    Inventors: CHANG-HSIEH YAO, HSUN-WEI CHIANG, CHIA-CHIEN CHANG, HSIN-YI PAI, CHUN-CHIA JUAN
  • Patent number: 11956563
    Abstract: A method for identifying video signal source is provided. The method includes the following steps. A first identification code is assigned to a first transmitter device by a receiver control unit of a receiver device. A first video data is transmitted by the first transmitter device. The first video data and a first identification image corresponding to the first identification code are combined as a first combined video data by the receiver control unit. The first combined video data is outputted to a display device by the receiver control unit.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: April 9, 2024
    Assignee: BenQ Corporation
    Inventors: Chia-Nan Shih, Chen-Chi Wu, Lin-Yuan You, Chin-Fu Chiang, Ron-Kun Tseng, Chuang-Wei Wu
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11935854
    Abstract: A method for forming a bonded semiconductor structure is disclosed. A first device wafer having a first bonding layer and a first bonding pad exposed from the first bonding layer and a second device wafer having a second bonding layer and a second bonding pad exposed from the second bonding layer are provided. Following, a portion of the first bonding pad is removed until a sidewall of the first bonding layer is exposed, and a portion of the second bonding layer is removed to expose a sidewall of the second bonding pad. The first device wafer and the second device wafer are then bonded to form a dielectric bonding interface between the first bonding layer and the second bonding layer and a conductive bonding interface between the first bonding pad and the second bonding pad. The conductive bonding interface and the dielectric bonding interface comprise a step-height.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: March 19, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Sung Chiang, Chia-Wei Liu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Publication number: 20240071954
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20240071953
    Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
  • Publication number: 20230187555
    Abstract: A semiconductor device, including a substrate, a semiconductor structure, a first gate dielectric layer, a first gate, a source, and a drain, is provided. The semiconductor structure includes a first metal oxide layer and a second metal oxide layer. The second metal oxide layer covers a top surface and a sidewall of the first metal oxide layer. The second metal oxide layer has a stepped structure at the sidewall of the first metal oxide layer. A carrier mobility of the first metal oxide layer is greater than a carrier mobility of a channel region of the second metal oxide layer. A thickness of the second metal oxide layer is greater than or equal to a thickness of the first metal oxide layer. A difference between a width of the first gate and a width of the first metal oxide layer is less than 0.5 ?m.
    Type: Application
    Filed: August 4, 2022
    Publication date: June 15, 2023
    Applicant: AUO Corporation
    Inventors: Chia-Wei Chiang, Yang-Shun Fan, Chen-Shuo Huang
  • Publication number: 20200357770
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a top semiconductor die, a bottom semiconductor die, a first encapsulant, a second encapsulant, a third encapsulant, a first redistribution layer and a second redistribution layer. The top semiconductor die is stacked on the bottom semiconductor die. The bottom semiconductor die is laterally encapsulated by the third encapsulant, and the third encapsulant is laterally surrounded by the first encapsulant. The top semiconductor die is laterally encapsulated by the second encapsulant. The first redistribution layer is disposed between the top and bottom semiconductor dies. The bottom semiconductor die, the first encapsulant and the third encapsulant are located between the first and second redistribution layers.
    Type: Application
    Filed: May 8, 2019
    Publication date: November 12, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Chia-Wei Chiang, Li-Chih Fang, Wen-Jeng Fan
  • Publication number: 20200243449
    Abstract: A package structure includes a redistribution structure, a bridge die, a plurality of conductive pillars, at least two dies, and an insulating encapsulant. The bridge die provides an electrical connection between the at least two dies. The conductive pillars provide an electrical connection between the at least two dies and the redistribution structure. The insulating encapsulant is disposed on the redistribution structure, encapsulates the bridge die and the conductive pillars, and covers each of the at least two dies. The bridge die of the package structure may be used to route signals between the at least two dies, allowing for a higher density of interconnecting routes between the at least two dies.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 30, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Chia-Wei Chiang, Li-Chih Fang, Wen-Jeng Fan
  • Publication number: 20200243461
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a bumpless die including a plurality of conductive pads, a conductive connector disposed aside the bumpless die and electrically coupled to the bumpless die, an insulating encapsulation encapsulating the bumpless die and the conductive connector, a circuit layer electrically connected to the bumpless die and the conductive connector, and a front side redistribution layer disposed on the circuit layer and including a finer line and spacing routing than the circuit layer. The circuit layer includes a conductive pattern disposed on the insulating encapsulation and extending along a thickness direction of the bumpless die to be connected to the conductive pads of the bumpless die, and a dielectric pattern disposed on the insulating encapsulation and laterally covering the conductive pattern.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 30, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Chia-Wei Chiang, Li-Chih Fang, Wen-Jeng Fan
  • Patent number: 10607860
    Abstract: A package structure including a die, a plurality of first conductive connectors, a second conductive connector electrically insulated from the die, a redistribution layer and a conductive shield is provided. The die includes an active surface, a back surface opposite the active surface, and a sidewall coupling the active surface to the back surface. The first conductive connectors are disposed on the active surface of the die and electrically connected to the die. The second conductive connector is disposed on the die and aside the first conductive connectors. The redistribution layer is disposed on the die and electrically connected to the first conductive connectors and the second conductive connector. The conductive shield coupled to the redistribution layer surrounds the second conductive connector and at least a portion of the sidewall. The die is electrically insulated to the conductive shield. A chip package structure is also provided.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: March 31, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Chia-Wei Chiang, Li-Chih Fang, Ji-Cheng Lin, Che-Min Chu, Chun-Te Lin
  • Patent number: 10593629
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a conductive casing, a semiconductor die, a conductive connector, an insulating encapsulant, a redistribution structure, and a first conductive terminal. The conductive casing has a cavity. The semiconductor die is disposed in the cavity of the conductive casing. The conductive connector is disposed on a periphery of the conductive casing. The insulating encapsulant encapsulates the conductive connector, the semiconductor die and the cavity. The redistribution structure is formed on the insulating encapsulant and is electrically connected to the conductive connector and the semiconductor die. The first conductive terminal is disposed in openings of the redistribution structure and is physically in contact with a portion of the conductive casing.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: March 17, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Chia-Wei Chiang, Li-Chih Fang, Wen-Jeng Fan
  • Publication number: 20200013721
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a conductive casing, a semiconductor die, a conductive connector, an insulating encapsulant, a redistribution structure, and a first conductive terminal. The conductive casing has a cavity. The semiconductor die is disposed in the cavity of the conductive casing. The conductive connector is disposed on a periphery of the conductive casing. The insulating encapsulant encapsulates the conductive connector, the semiconductor die and the cavity. The redistribution structure is formed on the insulating encapsulant and is electrically connected to the conductive connector and the semiconductor die. The first conductive terminal is disposed in openings of the redistribution structure and is physically in contact with a portion of the conductive casing.
    Type: Application
    Filed: July 9, 2018
    Publication date: January 9, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Chia-Wei Chiang, Li-Chih Fang, Wen-Jeng Fan
  • Publication number: 20200006274
    Abstract: A semiconductor package includes a semiconductor die, a first redistribution structure, a conductive structure, and an insulating encapsulant. The first redistribution structure includes a dielectric protrusion. The first redistribution structure includes a die attach region and a peripheral region surrounding the die attach region. The semiconductor die is disposed on the first redistribution structure within the die attach region. The dielectric protrusion is disposed in the peripheral region and extends in a thickness direction of the semiconductor die. The conductive structure is disposed on the first redistribution structure within the in the peripheral region and encapsulates the semiconductor dielectric protrusion. The conductive structure is electrically coupled to the first redistribution structure and the semiconductor die. The insulator is disposed on the first redistribution structure and encapsulates the semiconductor die and the conductive structure.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Chia-Wei Chiang, Li-Chih Fang, Wen-Jeng Fan
  • Patent number: 10431549
    Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: October 1, 2019
    Assignee: Powertech Technology Inc.
    Inventors: Chien-Wen Huang, Chia-Wei Chiang, Wen-Jeng Fan, Li-Chih Fang
  • Publication number: 20190214347
    Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Chien-Wen Huang, Chia-Wei Chiang, Wen-Jeng Fan, Li-Chih Fang
  • Patent number: 10276510
    Abstract: A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 30, 2019
    Assignee: Powertech Technology Inc.
    Inventors: Chia-Wei Chiang, Li-Chih Fang, Ji-Cheng Lin, Che-Min Chu, Chun-Te Lin
  • Publication number: 20190096821
    Abstract: A manufacturing method of a package structure including the following steps is provided. A plurality of first conductive connectors and a second conductive connector on an active surface of a die are formed. The first conductive connectors are electrically connected to the die. The second conductive connector is formed aside the first conductive connectors and electrically insulated to the die. A redistribution layer is formed on the die. The redistribution layer is electrically connected to the first conductive connectors and the second conductive connector. A conductive shield is formed on the redistribution layer to surround the second conductive connector and at least a portion of a sidewall of the die coupled the active surface. The die is electrically insulated from the conductive shield. Another manufacturing method of a package structure is also provided.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 28, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Chia-Wei Chiang, Li-Chih Fang, Ji-Cheng Lin, Che-Min Chu, Chun-Te Lin
  • Publication number: 20190096699
    Abstract: A package structure including a die, a plurality of first conductive connectors, a second conductive connector electrically insulated from the die, a redistribution layer and a conductive shield is provided. The die includes an active surface, a back surface opposite the active surface, and a sidewall coupling the active surface to the back surface. The first conductive connectors are disposed on the active surface of the die and electrically connected to the die. The second conductive connector is disposed on the die and aside the first conductive connectors. The redistribution layer is disposed on the die and electrically connected to the first conductive connectors and the second conductive connector. The conductive shield coupled to the redistribution layer surrounds the second conductive connector and at least a portion of the sidewall. The die is electrically insulated to the conductive shield. A chip package structure is also provided.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 28, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Chia-Wei Chiang, Li-Chih Fang, Ji-Cheng Lin, Che-Min Chu, Chun-Te Lin