Patents by Inventor Chia Wei CHOU
Chia Wei CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153890Abstract: The semiconductor package substrate module including a substrate, a plurality of first wires, at least one second wire, a chip, and an encapsulating body, wherein the first wires electrically connect to a first electrical contact point of the substrate and a second electrical contact point of the chip. Besides, one end of the at least one second wire connects to the at least one grounding transfer area or a first ground contact point of the substrate, and another end of the second wire extends toward a cutting area. The encapsulating body encapsulates the substrate, the first and second wires, and the chip. The semiconductor package substrate module is cut and separated along the cutting area of the substrate to form a plurality of semiconductor packaging components. A side surface of the encapsulating body exposes the first wires or at least one second wire of each semiconductor packaging component.Type: ApplicationFiled: March 30, 2023Publication date: May 9, 2024Inventors: Chia Fong CHOU, Ta Wei CHOU, Hui-Lung HSU
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Patent number: 11955397Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.Type: GrantFiled: November 9, 2020Date of Patent: April 9, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
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Publication number: 20230242594Abstract: Provided herein are engineered Coronavirus S proteins, such as engineered SARS-CoV-2 S proteins. In some aspects, the engineered S proteins exhibit enhanced conformational stability and/or antigenicity. Methods are also provided for use of engineered proteins as diagnostics, in screening platforms and/or in vaccine compositions.Type: ApplicationFiled: May 28, 2021Publication date: August 3, 2023Applicants: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM, THE TRUSTEES OF DARTMOUTH COLLEGEInventors: Jason MCLELLAN, Jennifer MAYNARD, Andrea CHASSE, Ilya FINKELSTEIN, Mohammad JAVANMARDI, Jeffrey SCHAUB, Hung-Che KUO, Chia-Wei CHOU, Jory GOLDSMITH, Christy HJORTH, Ching-Lin HSIEH, Patrick BYRNE, Nicole JOHNSON, Nianshuang WANG, Daniel WRAPP
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Patent number: 11431268Abstract: A motor driving system includes a controller, motors and motor drivers. In the normal supplying state of a power supply, the controller controls the motor drivers. The motor drivers output driving signals for driving the motors respectively. In an abnormal state or a power-off state of the power supply, one of the motor drivers is set to be a master driver and the others are set to be slave driver. The master driver activates a deceleration energy backup (DEB) function, powers the slave drivers through a common-DC-bus structure, controls the slave drivers, and during deceleration maintains a ratio between frequencies of the driving signals, until all of the motors are decelerated to stop at the same time.Type: GrantFiled: May 11, 2021Date of Patent: August 30, 2022Assignee: DELTA ELECTRONICS, INC.Inventors: Cheng-Yun Lin, Chia-Wei Chou, Chen-Hsiang Kuo
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Publication number: 20220069744Abstract: A motor driving system includes a controller, motors and motor drivers. In the normal supplying state of a power supply, the controller controls the motor drivers. The motor drivers output driving signals for driving the motors respectively. In an abnormal state or a power-off state of the power supply, one of the motor drivers is set to be a master driver and the others are set to be slave driver. The master driver activates a deceleration energy backup (DEB) function, powers the slave drivers through a common-DC-bus structure, controls the slave drivers, and during deceleration maintains a ratio between frequencies of the driving signals, until all of the motors are decelerated to stop at the same time.Type: ApplicationFiled: May 11, 2021Publication date: March 3, 2022Inventors: Cheng-Yun LIN, Chia-Wei CHOU, Chen-Hsiang KUO
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Patent number: 10470323Abstract: A hinge structure includes a first base, a second base, a first linking rod, a second linking rod, and a torque assembly. The first linking rod has a first pivot part, a first sliding part, and a second pivot part. The first pivot part is pivoted to the first base, and the first sliding part is slidably connected to the second base. The second linking rod has a second sliding part, a shaft part, a third pivot part, and a fourth pivot part. The second sliding part is slidably connected to the first base. The third pivot part is pivoted to the second base. The second pivot part is pivoted to the fourth pivot part. The torque assembly has a sleeve part sleeved on the shaft part and a connection part connected to the second base. The sleeve part generates torque during rotation with respect to the shaft part.Type: GrantFiled: July 16, 2018Date of Patent: November 5, 2019Assignee: COMPAL ELECTRONICS, INC.Inventors: Hsien-Hung Cheng, You-Yu Chen, Chia-Wei Chou, Po-Yi Chang, Cheng-Yo Hsiao, Wei-Ting Liu
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Patent number: 10263089Abstract: A transistor including a substrate, a gate layer, a first insulating layer, an active layer, a source and a drain is provided. The gate layer is disposed on the first insulating layer, and has a plurality of first through holes. The first insulating layer covers the gate layer and a part of the substrate exposed by the first through holes, and forms a plurality of recesses respectively corresponding to the first through holes. The active layer is disposed on the first insulating layer, and has a plurality of second through holes. The second through holes communicate with the recesses, respectively. The source is disposed on a part of the active layer. The drain is disposed on another part of the active layer. A manufacturing method of the transistor is also provided.Type: GrantFiled: May 8, 2015Date of Patent: April 16, 2019Assignee: E Ink Holdings Inc.Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chia-Wei Chou, Cheng-Hang Hsu
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Publication number: 20190021179Abstract: A hinge structure includes a first base, a second base, a first linking rod, a second linking rod, and a torque assembly. The first linking rod has a first pivot part, a first sliding part, and a second pivot part. The first pivot part is pivoted to the first base, and the first sliding part is slidably connected to the second base. The second linking rod has a second sliding part, a shaft part, a third pivot part, and a fourth pivot part. The second sliding part is slidably connected to the first base. The third pivot part is pivoted to the second base. The second pivot part is pivoted to the fourth pivot part. The torque assembly has a sleeve part sleeved on the shaft part and a connection part connected to the second base. The sleeve part generates torque during rotation with respect to the shaft part.Type: ApplicationFiled: July 16, 2018Publication date: January 17, 2019Applicant: COMPAL ELECTRONICS, INC.Inventors: Hsien-Hung Cheng, You-Yu Chen, Chia-Wei Chou, Po-Yi Chang, Cheng-Yo Hsiao, Wei-Ting Liu
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Publication number: 20160064499Abstract: A transistor including a substrate, a gate layer, a first insulating layer, an active layer, a source and a drain is provided. The gate layer is disposed on the first insulating layer, and has a plurality of first through holes. The first insulating layer covers the gate layer and a part of the substrate exposed by the first through holes, and forms a plurality of recesses respectively corresponding to the first through holes. The active layer is disposed on the first insulating layer, and has a plurality of second through holes. The second through holes communicate with the recesses, respectively. The source is disposed on a part of the active layer. The drain is disposed on another part of the active layer. A manufacturing method of the transistor is also provided.Type: ApplicationFiled: May 8, 2015Publication date: March 3, 2016Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chia-Wei Chou, Cheng-Hang Hsu
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Patent number: 8923027Abstract: A five-level DC-AC converter includes a capacitor set and a full-bridge circuit. The capacitor set contains two DC capacitors, a power electronic switch and two diodes. When the power electronic switch is turned on/off, the two DC capacitors are connected in series/parallel to provide a two-level DC voltage to the full-bridge circuit. The full-bridge circuit further converts the two-level DC voltage to output a voltage with three voltage levels in the positive half cycle and three voltage levels in the negative half cycle. This achieves the goal of using five power electronic switches to convert DC power into AC power with five voltage levels.Type: GrantFiled: February 13, 2012Date of Patent: December 30, 2014Assignee: Ablerex Electronics Co., Ltd.Inventors: Chin-Chang Wu, Wen-Jung Chiang, Ming-Pin Mai, Chia-Wei Chou, Mao-Jang He
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Publication number: 20130033912Abstract: A five-level DC-AC converter includes a capacitor set and a full-bridge circuit. The capacitor set contains two DC capacitors, a power electronic switch and two diodes. When the power electronic switch is turned on/off, the two DC capacitors are connected in series/parallel to provide a two-level DC voltage to the full-bridge circuit. The full-bridge circuit further converts the two-level DC voltage to output a voltage with three voltage levels in the positive half cycle and three voltage levels in the negative half cycle. This achieves the goal of using five power electronic switches to convert DC power into AC power with five voltage levels.Type: ApplicationFiled: February 13, 2012Publication date: February 7, 2013Inventors: Chin-Chang Wu, Wen-Jung Chiang, Ming-Pin Mai, Chia-Wei Chou, Mao-Jang He
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Publication number: 20120088653Abstract: A method of providing solar cell electrode by electroless plating and an activator used therein are disclosed. The method of the present invention can be performed without silver paste, and comprises steps: (A) providing a silicon substrate; (B) contacting the silicon substrate with an activator, wherein the activator comprises: a noble metal or a noble metal compound, a thickening agent, and water; (C) washing the silicon substrate by a cleaning agent; (D) dipping the silicon substrate in an electroless nickel plating solution to perform electroless plating. The method of providing solar cell electrode by electroless plating of the present invention has high selectivity between silicon nitride and silicon, large working window, and is steady, easily to be controlled, therefore is suitable for being used in the fabrication of the electrodes of the solar cell substrate.Type: ApplicationFiled: December 20, 2011Publication date: April 12, 2012Applicant: E-CHEM ENTERPRISE CORP.Inventors: Chia Wei CHOU, Su-Fei Hsu, Michael Liu
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Publication number: 20110192316Abstract: An electroless nickel plating solution for solar cell electrode, which comprises SiNx and Si patterned structure, is disclosed. The electroless plating solution of the present invention comprises: nickel ion; a reducing agent; a first chelating agent; a second chelating agent; and water. The electroless plating solution of the present invention has high selectivity between Si and SiNx and is harmless to the aluminum-based layer, therefore is suitable for being used in the fabrication of the electrodes of the solar cell.Type: ApplicationFiled: January 26, 2011Publication date: August 11, 2011Applicant: E-CHEM ENTERPRISE CORP.Inventors: Chia Wei CHOU, Su-Fei HSU, Michael LIU
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Publication number: 20110195542Abstract: A method of providing solar cell electrode by electroless plating and an activator used therein are disclosed. The method of the present invention can be performed without silver paste, and comprises steps: (A) providing a silicon substrate; (B) contacting the silicon substrate with an activator, wherein the activator comprises: a noble metal or a noble metal compound, a thickening agent, and water; (C) washing the silicon substrate by a cleaning agent; (D) dipping the silicon substrate in an electroless nickel plating solution to perform electroless plating. The method of providing solar cell electrode by electroless plating of the present invention has high selectivity between silicon nitride and silicon, large working window, and is steady, easily to be controlled, therefore is suitable for being used in the fabrication of the electrodes of the solar cell substrate.Type: ApplicationFiled: January 26, 2011Publication date: August 11, 2011Applicant: E-CHEM ENTERPRISE CORP.Inventors: Chia Wei Chou, Su-Fei Hsu, Michael Liu