Abstract: A three-dimensional reflective display device includes a reflective display panel, a lens array disposed on the reflective display panel, and a front light module disposed on the lens array. The reflective display panel includes pixel structures, and each pixel structure includes a left-eye pixel and a right-eye pixel. The lens array includes lenticular lenses extending in a first direction and arranged in a second direction perpendicular to the first direction. The lenticular lenses are respectively corresponding to the pixel structures. The front light module includes two front light components. The two front light components both include a light guide plate and a light source disposed on a light incident surface of the light guide plate, where the light incident surfaces face to each other in the second direction.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.

Abstract: An anomaly detection model training method, anomaly detection methods, and load detection devices for household electricity are provided. The anomaly detection method is applied to the load detection device, which includes a processing unit and an anomaly detection model. The processing unit trains the anomaly detection model and performs an anomaly detection method.

Abstract: A method for facilitating streamer interaction with a viewer includes extracting a history topic based on an activity record of the viewer; calculating a score of each of the history topics based on at least one parameter; and generating a topic suggestion based on the history topic and the score which is corresponding to the history topic, and providing the topic suggestion to the streamer. The method is suitable for providing a topic suggestion (or interact topic suggestion) with respect to the viewer to the streamer via a live-streaming platform executed by a computing device. Thereby, the method can be used for facilitating streamer interaction with viewers and provides an appropriate topic suggestion. In addition, a computing device and a computer-readable storage medium which are capable of implementing the method are also provided.

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.

Abstract: An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.

Abstract: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.

Abstract: An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.

Abstract: An electrostatic discharge protection device coupled between a first power line and a second power line is provided. A first N-type doped region is formed in a P-type well. A first P-type doped region is formed in the first N-type doped region. A second P-type doped region includes a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. A second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT).

Abstract: An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.

Abstract: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.

Abstract: An electrostatic discharge protection device is coupled between a first power line and a second power line and comprises a P-type well, a first N-type doped region, a first P-type doped region, a second P-type doped region and a second N-type doped region. The first N-type doped region is formed in the P-type well. The first P-type doped region is formed in the first N-type doped region. The second P-type doped region comprises a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. The second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT).