Patents by Inventor Chia-Wei Hung

Chia-Wei Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12288811
    Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming an n-type work function layer in a gate trench in a gate structure, wherein the n-type work function layer is formed around first channel layers in a p-type gate region and around second channel layers in an n-type gate region, forming a first metal fill layer in a first gate trench over the n-type work function layer in the p-type gate region and in a second gate trench over the n-type work function layer in the n-type gate region, removing the first metal fill layer from the p-type gate region, removing the n-type work function layer from the p-type gate region, forming a p-type work function layer in the first gate trench of the p-type gate region, and forming a second metal fill layer in the first gate trench of the p-type gate region.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: April 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hang Chiu, Kuan-Ting Liu, Chi On Chui, Chia-Wei Chen, Jian-Hao Chen, Cheng-Lung Hung
  • Patent number: 12289668
    Abstract: A Bluetooth audio broadcasting system includes: an audio broadcasting device arranged to operably broadcast BLE (Bluetooth Low Energy) audio packets; a first Bluetooth member device arranged to operably parse the BLE audio packets to acquire a predetermined audio data and to operably control a first audio playback circuit to playback the predetermined audio data; a second Bluetooth member device arranged to operably parse the BLE audio packets to acquire the predetermined audio data and to operably control a second audio playback circuit to playback the predetermined audio data; and a host device arranged to operably generate and transmit a target control command to the first and second Bluetooth member devices when the host device receives an alert signal, or when a specific ambient sound occurs in the surrounding environment of the host device.
    Type: Grant
    Filed: May 3, 2024
    Date of Patent: April 29, 2025
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yi-Cheng Chen, Bi Wei, Yu Hsuan Liu, Chia Chun Hung
  • Patent number: 12289666
    Abstract: A Bluetooth audio broadcasting system includes: an audio broadcasting device arranged to operably broadcast BLE (Bluetooth Low Energy) audio packets; a first Bluetooth member device arranged to operably parse the BLE audio packets to acquire a predetermined audio data and to operably control a first audio playback circuit to playback the predetermined audio data; and a second Bluetooth member device arranged to operably parse the BLE audio packets to acquire the predetermined audio data and to operably control a second audio playback circuit to playback the predetermined audio data. When the first or second Bluetooth member device receives an alert signal, or when a specific ambient sound occurs in the surrounding environment of the first or second Bluetooth member device, the audio broadcasting device utilizes a target control command to instruct the first and second Bluetooth member devices to synchronously reduce their volume to be lower than a predetermined threshold.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: April 29, 2025
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yi-Cheng Chen, Bi Wei, Yu Hsuan Liu, Chia Chun Hung
  • Patent number: 12289667
    Abstract: A Bluetooth audio broadcasting system includes: an audio broadcasting device arranged to operably broadcast BLE (Bluetooth Low Energy) audio packets; a first Bluetooth member device arranged to operably parse the BLE audio packets to acquire a predetermined audio data and to operably control a first audio playback circuit to playback the predetermined audio data; a second Bluetooth member device arranged to operably parse the BLE audio packets to acquire the predetermined audio data and to operably control a second audio playback circuit to playback the predetermined audio data; and a host device arranged to operably generate and transmit a target control command to the first and second Bluetooth member devices when the first or second Bluetooth member device receives an alert signal, or when a specific ambient sound occurs in the surrounding environment of the first or second Bluetooth member device.
    Type: Grant
    Filed: May 3, 2024
    Date of Patent: April 29, 2025
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yi-Cheng Chen, Bi Wei, Yu Hsuan Liu, Chia Chun Hung
  • Publication number: 20250125611
    Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Li-Wei Chu, Tao Yi Hung, Chia-Hui Chen, Wun-Jie Lin, Jam-Wem Lee
  • Publication number: 20250126769
    Abstract: An electronic memory device includes a memory-cell circuit. The electronic memory device also includes a non-memory-cell circuit. The non-memory cell circuit includes an active region. The active region extends in a first direction in a top view. The active region includes a first segment and a second segment. The first segment has a first dimension measured in a second direction in the top view. The second segment has a second dimension measured in the second direction different from the first direction in the top view. The second dimension is different from the first dimension.
    Type: Application
    Filed: January 12, 2024
    Publication date: April 17, 2025
    Inventors: Chia-Hao Pao, Ping-Wei Wang, Lien-Jung Hung, Feng-Ming Chang, Yu-Kuan Lin, Jui-Wen Chang
  • Publication number: 20250126883
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Application
    Filed: December 23, 2024
    Publication date: April 17, 2025
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Patent number: 12271654
    Abstract: An audio dose monitoring circuit includes: a sound level measuring circuit arranged to operably generate multiple sound level values, wherein the multiple sound level values respectively correspond to the sound levels generated by an audio playback device at multiple time points or the sound levels received by a microphone at multiple time points; an audio dose calculating circuit coupled with the sound level measuring circuit and arranged to operably generate an audio dose value corresponding to a measuring period based on the multiple sound level values and contents of a weighting table; a control circuit coupled with the audio dose calculating circuit and arranged to operably compare the audio dose value with a dose threshold to determine whether to generate a control signal or not; and an indication signal generating circuit coupled with the control circuit and arranged to operably generate a corresponding indication signal according to the control signal.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: April 8, 2025
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yu Wei Liu, Chi Wu, Chia Chun Hung
  • Publication number: 20250110307
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: December 12, 2024
    Publication date: April 3, 2025
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Publication number: 20250085562
    Abstract: A three-dimensional reflective display device includes a reflective display panel, a lens array disposed on the reflective display panel, and a front light module disposed on the lens array. The reflective display panel includes pixel structures, and each pixel structure includes a left-eye pixel and a right-eye pixel. The lens array includes lenticular lenses extending in a first direction and arranged in a second direction perpendicular to the first direction. The lenticular lenses are respectively corresponding to the pixel structures. The front light module includes two front light components. The two front light components both include a light guide plate and a light source disposed on a light incident surface of the light guide plate, where the light incident surfaces face to each other in the second direction.
    Type: Application
    Filed: September 5, 2024
    Publication date: March 13, 2025
    Inventors: Shin-Bo LIN, Jen-Yuan CHI, Yu-Nan PAO, Chia-Ming HSIEH, Sheng-Wei CHEN, Chi-Mao HUNG
  • Patent number: 12243872
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Huang Huang, Yu-Ling Cheng, Shun-Hui Yang, An Chyi Wei, Chia-Jen Chen, Shang-Shuo Huang, Chia-I Lin, Chih-Chang Hung
  • Publication number: 20250068884
    Abstract: An anomaly detection model training method, anomaly detection methods, and load detection devices for household electricity are provided. The anomaly detection method is applied to the load detection device, which includes a processing unit and an anomaly detection model. The processing unit trains the anomaly detection model and performs an anomaly detection method.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 27, 2025
    Inventors: Kuang Ping Tseng, Wen Jen Ho, Chia Wei Tsai, Kuei Chun Chiang, Yung Chieh Hung
  • Publication number: 20250047919
    Abstract: A method for facilitating streamer interaction with a viewer includes extracting a history topic based on an activity record of the viewer; calculating a score of each of the history topics based on at least one parameter; and generating a topic suggestion based on the history topic and the score which is corresponding to the history topic, and providing the topic suggestion to the streamer. The method is suitable for providing a topic suggestion (or interact topic suggestion) with respect to the viewer to the streamer via a live-streaming platform executed by a computing device. Thereby, the method can be used for facilitating streamer interaction with viewers and provides an appropriate topic suggestion. In addition, a computing device and a computer-readable storage medium which are capable of implementing the method are also provided.
    Type: Application
    Filed: January 24, 2024
    Publication date: February 6, 2025
    Inventors: YUNG-CHI HSU, CHI-WEI LIN, SHAO-TANG CHIEN, WEI-HSIANG HUNG, WEI-KUN LU, YU-CHENG FAN, CHIA-HAN CHANG, HUNG-KUANG TAI
  • Patent number: 12218130
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Patent number: 12219747
    Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Chih-Hsuan Chen, Kian-Long Lim, Chao-Yuan Chang, Feng-Ming Chang, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 12204163
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: January 21, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 10319713
    Abstract: An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 11, 2019
    Assignee: LEADTREND TECHNOLOGY CORPORATION
    Inventors: Kuo-Chin Chiu, Chia-Wei Hung
  • Publication number: 20180211950
    Abstract: An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 26, 2018
    Inventors: Kuo-Chin Chiu, Chia-Wei Hung
  • Patent number: 8507946
    Abstract: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: August 13, 2013
    Assignees: Vanguard International Semiconductor Corporation, National Chiao Tung University
    Inventors: Yeh-Jen Huang, Yeh-Ning Jou, Ming-Dou Ker, Wen-Yi Chen, Chia-Wei Hung, Hwa-Chyi Chiou
  • Patent number: 8278715
    Abstract: An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: October 2, 2012
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yeh-Ning Jou, Chia-Wei Hung, Hwa-Chyi Chiou, Yeh-Jen Huang, Shu-Ling Chang