Patents by Inventor Chia-Wei Hung
Chia-Wei Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11981736Abstract: Antibodies that selectively bind to glycosylated PD-1 relative to unglycosylated PD-1 are provided. In some aspects, PD-1 polypeptides comprising glycosylated amino acid positions are also provided. Methods for making and using such antibodies and polypeptides (e.g., for the treatment of cancer) are also provided.Type: GrantFiled: November 13, 2020Date of Patent: May 14, 2024Assignees: ST CUBE INC., BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEMInventors: Stephen S. Yoo, Ezra M. Chung, Yong-Soo Kim, Seung-Oe Lim, Chia-Wei Li, Mien-Chie Hung
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Patent number: 11980016Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.Type: GrantFiled: July 20, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chuan Yang, Chia-Hao Pao, Yu-Kuan Lin, Lien-Jung Hung, Ping-Wei Wang, Shih-Hao Lin
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Publication number: 20240123479Abstract: A recycling apparatus for a solar cell module includes a platform for supporting and positioning the solar cell module, and at least one milling device disposed on the platform and having a milling member configured to contact a back plate of the solar cell module, and a casing defining a chip-receiving space and having an air inlet and a suction port communicating with the chip-receiving space. A drive device is connected to the at least one milling device for driving the at least one milling device to move around and mill the solar cell module through the milling member.Type: ApplicationFiled: October 28, 2021Publication date: April 18, 2024Applicant: NATIONAL UNIVERSITY OF TAINANInventors: Yao-Hsien FU, Hsueh-Pin TAI, Chia-Tsung HUNG, Cheng-Chen LIU, Chun-Chih HU, How-Wei KE
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Publication number: 20240113113Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11933786Abstract: Antibodies that selectively bind to glycosylated PD-1 relative to unglycosylated PD-1 are provided. In some aspects, PD-1 polypeptides comprising glycosylated amino acid positions are also provided. Methods for making and using such antibodies and polypeptides (e.g., for the treatment of cancer) are also provided.Type: GrantFiled: November 13, 2020Date of Patent: March 19, 2024Assignees: STCUBE, INC., BOARD OF REGENTS, THE UNIVERSITY OF TEXASInventors: Stephen S. Yoo, Ezra M. Chung, Yong-Soo Kim, Mien-Chie Hung, Chia-Wei Li, Seung-Oe Lim
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Publication number: 20240088650Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Li-Wei Chu, Tao Yi Hung, Chia-Hui Chen, Wun-Jie Lin, Jam-Wem Lee
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Patent number: 11929314Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.Type: GrantFiled: March 12, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
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Publication number: 20240080117Abstract: The present invention provides a wireless communication method of an electronic device, wherein the electronic device includes a first radio and a second radio, a maximum bandwidth or a maximum. NSS supported by the first radio is different from a maximum bandwidth or a maximum NSS supported by the second radio. The wireless communication method includes the step of: using the first radio to communicate with another electronic device; determining if parameters of the electronic device satisfy a condition; and in response to the parameters of the electronic device satisfying the condition, enabling the second radio and using the second radio to communicate with the another electronic device, and disabling the first radio.Type: ApplicationFiled: August 9, 2023Publication date: March 7, 2024Applicant: MEDIATEK INC.Inventors: Ying-You Lin, Jun-Wei Lin, Ren-Fang Gan, Ding-Yuh Hwang, Po-Ting Kao, Chia-Ning Chang, Ssu-Ying Hung
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Patent number: 10319713Abstract: An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.Type: GrantFiled: January 11, 2018Date of Patent: June 11, 2019Assignee: LEADTREND TECHNOLOGY CORPORATIONInventors: Kuo-Chin Chiu, Chia-Wei Hung
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Publication number: 20180211950Abstract: An embodiment provides a semiconductor device integrated with a switch device and an ESD protection device, having electrostatic discharge robustness. Formed on a semiconductor substrate of a first type is a drain region of a second type opposite to the first type. The switch device has a source region of the second type, formed on the semiconductor substrate and with a first arch portion facing inwardly toward a first direction. The first arch portion partially surrounds the drain region. A control gate of the switch device controls electric connection between the drain region and the source region. The ESD protection device comprises a first region and a second region, both of the first type. The first region adjoins the drain region. The second region has a second arch portion facing inwardly toward a second direction opposite to the first direction, and the second arch portion partially surrounds the first region.Type: ApplicationFiled: January 11, 2018Publication date: July 26, 2018Inventors: Kuo-Chin Chiu, Chia-Wei Hung
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Patent number: 8507946Abstract: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.Type: GrantFiled: March 4, 2011Date of Patent: August 13, 2013Assignees: Vanguard International Semiconductor Corporation, National Chiao Tung UniversityInventors: Yeh-Jen Huang, Yeh-Ning Jou, Ming-Dou Ker, Wen-Yi Chen, Chia-Wei Hung, Hwa-Chyi Chiou
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Patent number: 8278715Abstract: An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.Type: GrantFiled: February 2, 2011Date of Patent: October 2, 2012Assignee: Vanguard International Semiconductor CorporationInventors: Yeh-Ning Jou, Chia-Wei Hung, Hwa-Chyi Chiou, Yeh-Jen Huang, Shu-Ling Chang
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Patent number: 8278736Abstract: An electrostatic discharge protection device coupled between a first power line and a second power line is provided. A first N-type doped region is formed in a P-type well. A first P-type doped region is formed in the first N-type doped region. A second P-type doped region includes a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. A second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT).Type: GrantFiled: September 3, 2010Date of Patent: October 2, 2012Assignee: Vanguard International Semiconductor CorporationInventors: Yeh-Ning Jou, Chia-Wei Hung, Shu-Ling Chang, Hwa-Chyi Chiou, Yeh-Jen Huang
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Publication number: 20120193718Abstract: An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.Type: ApplicationFiled: February 2, 2011Publication date: August 2, 2012Inventors: Yeh-Ning JOU, Chia-Wei Hung, Hwa-Chyi Chiou, Yeh-Jen Huang, Shu-Ling Chang
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Publication number: 20120146151Abstract: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.Type: ApplicationFiled: March 4, 2011Publication date: June 14, 2012Inventors: Yeh-Jen HUANG, Yeh-Ning Jou, Ming-Dou Ker, Wen-Yi Chen, Chia-Wei Hung, Hwa-Chyi Chiou
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Publication number: 20120056239Abstract: An electrostatic discharge protection device is coupled between a first power line and a second power line and comprises a P-type well, a first N-type doped region, a first P-type doped region, a second P-type doped region and a second N-type doped region. The first N-type doped region is formed in the P-type well. The first P-type doped region is formed in the first N-type doped region. The second P-type doped region comprises a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. The second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT).Type: ApplicationFiled: September 3, 2010Publication date: March 8, 2012Inventors: Yeh-Ning JOU, Chia-Wei Hung, Shu-Ling Chang, Hwa-Chyi Chiou, Yeh-Jen Huang