Patents by Inventor Chia-Wei Liu

Chia-Wei Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220013715
    Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.
    Type: Application
    Filed: August 4, 2020
    Publication date: January 13, 2022
    Inventors: Chia-Wei Liu, Jia-Feng Fang, Chun-Hsien Lin
  • Patent number: 11127625
    Abstract: A method and structure for providing a semiconductor-on-insulator (SCOI) wafer having a buried low-K dielectric layer includes forming a device layer on a first semiconductor substrate. In various embodiments, at least a portion of the device layer is separated from the first semiconductor substrate, where the separating forms a cleaved surface on the separated portion of the device layer. In some examples, a patterned low-K dielectric layer is formed on a second semiconductor substrate. Thereafter, and in some embodiments, the separated portion of the device layer is bonded, along the cleaved surface, to the patterned low-K dielectric layer.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsiang Tsai, Chung-Chuan Tseng, Li Hsin Chu, Chia-Wei Liu
  • Publication number: 20210280783
    Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ming Wang, Chia-Wei Liu, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao, Huei-Tzu Wang
  • Publication number: 20210265425
    Abstract: A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first portion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.
    Type: Application
    Filed: April 27, 2021
    Publication date: August 26, 2021
    Inventors: Jheng-Hong JIANG, Cheung CHENG, Chia-Wei LIU
  • Patent number: 11038108
    Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ming Wang, Chia-Wei Liu, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao, Huei-Tzu Wang
  • Patent number: 11011576
    Abstract: A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first portion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jheng-Hong Jiang, Cheung Cheng, Chia-Wei Liu
  • Patent number: 10911072
    Abstract: Systems and methods for enabling a WLAN client to communicate simultaneously over more than one band at a time are described, where each client has at least one radio that is operational in each supported band. Load balancing based on traffic requirements optimizes the use of the multiple bands.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: February 2, 2021
    Assignee: NETGEAR, INC.
    Inventors: Peiman Amini, Joseph Amalan Arul Emmanuel, Chia-Wei Liu
  • Publication number: 20210013907
    Abstract: A simultaneous client wireless device includes wireless modules configured to perform communication functions of a PHY (physical) layer for wireless radios operable in different bands. The simultaneous client wireless device also includes a communication module configured as an intermediate layer between the PHY layer of the wireless modules and a network layer. The communication module is configured to use an application programming interface to retrieve information from the PHY layer and write information to the PHY layer of the wireless modules, perform communication functions of upper MAC (media access control) and lower MAC layers for the wireless bands, and manage simultaneous communications over the wireless bands. The communications over the wireless bands can use a local area network protocol.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Joseph Amalan Arul Emmanuel, Peiman Amini, Chia-Wei Liu
  • Publication number: 20200373487
    Abstract: The present disclosure is directed to a method for the formation of resistive random-access memory (RRAM) structures with a low profile between or within metallization layers. For example, the method includes forming, on a substrate, a first metallization layer with conductive structures and a first dielectric layer abutting sidewall surfaces of the conductive structures; etching a portion of the first dielectric layer to expose a portion of the sidewall surfaces of the conductive structures; depositing a memory stack on the first metallization layer, the exposed portion of the sidewall surfaces, and a top surface of the conductive structures; patterning the memory stack to form a memory structure that covers the exposed portion of the sidewall surfaces and the top surface of the conductive structures; depositing a second dielectric layer to encapsulate the memory stack; and forming a second metallization layer on the second dielectric layer.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ming Wang, Chia-Wei Liu, Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao, Huei-Tzu Wang
  • Patent number: 10819375
    Abstract: A simultaneous client wireless device includes wireless modules configured to perform communication functions of lower MAC (media access control) and PHY (physical) layers for wireless radios operable in multiple wireless bands. The simultaneous client wireless device also includes a communication module configured as an intermediate layer between the lower MAC layer of the wireless modules and a network layer. The communication module is configured to use an application programming interface to retrieve information from the lower MAC layer and write information to the lower MAC layer of each wireless module, perform communication functions of an upper MAC layer for the wireless bands, and manage simultaneous communications over the wireless bands. The communications over the wireless bands can use a local area network protocol.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: October 27, 2020
    Assignee: NETGEAR, INC.
    Inventors: Joseph Amalan Arul Emmanuel, Peiman Amini, Chia-Wei Liu
  • Patent number: 10818556
    Abstract: A method for forming a semiconductor structure is provided. Multiple fins extending along a first direction are formed in a semiconductor substrate. The multiple fins includes a group of active fins, a pair of protection fins sandwiching about the group the active fins, and at least one dummy fin around the pair of protection fins. A fin cut process is performed to remove the at least one dummy fin around the pair of protection fins. After performing the fin cut process, trench isolation structures are formed within the trenches between the multiple fins. The trench isolation structures are subjected to an anneal process. After annealing the trench isolation structures, the pair of protection fins is removed.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 27, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao-Yeh Liu, Jia-Feng Fang, Yu-Hsiang Lin, Ching-Hsiang Chiu, Chia-Wei Liu
  • Patent number: 10793542
    Abstract: The present invention provides a compound of formula (1): wherein X, Y, Z1, Z2, R1, R2, A, B, p and q are as disclosed in the specification. A pharmaceutical composition and a method for modulating the Hedgehog pathway are also provided. The present invention rurthe r provides a process for preparing the compound.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: October 6, 2020
    Assignee: DEVELOPMENT CENTER FOR BIOTECHNOLOGY
    Inventors: Mann-Yan Kuo, Ying-Shuan Lee, Yann-Yu Lu, Chia-Wei Liu, Seline Hsieh, Ju-Ying Yang
  • Publication number: 20200303243
    Abstract: A method for manufacturing a semiconductor structure includes at least following steps. A device layer is formed on a first semiconductor substrate. The device layer is separated from the first semiconductor substrate. A dielectric layer is formed on a second semiconductor substrate. The device layer is bonded onto the dielectric layer.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Yu-Hsiang TSAI, Chung-Chuan TSENG, Chia-Wei LIU, Li-Hsin CHU
  • Publication number: 20200194313
    Abstract: A method for forming a semiconductor structure is provided. Multiple fins extending along a first direction are formed in a semiconductor substrate. The multiple fins includes a group of active fins, a pair of protection fins sandwiching about the group the active fins, and at least one dummy fin around the pair of protection fins. A fin cut process is performed to remove the at least one dummy fin around the pair of protection fins. After performing the fin cut process, trench isolation structures are formed within the trenches between the multiple fins. The trench isolation structures are subjected to an anneal process. After annealing the trench isolation structures, the pair of protection fins is removed.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Hao-Yeh Liu, Jia-Feng Fang, Yu-Hsiang Lin, Ching-Hsiang Chiu, Chia-Wei Liu
  • Patent number: 10684067
    Abstract: A method for assembling a camera assembly for viewing in all directions inside a refrigerator, the refrigerator comprising a body, a door, and the camera assembly. The camera assembly comprises a locking base, a securing base, and a camera, the securing base being coupled to the locking base. The camera is coupled to the securing base, the securing base defines a slot for receiving the camera. The locking base is coupled to the door.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 16, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jung-Chun Yeh, Chia-Wei Liu
  • Patent number: 10679889
    Abstract: A method for manufacturing a semiconductor structure includes at least following steps. A device layer is formed on a first semiconductor substrate. The device layer is separated from the first semiconductor substrate. A dielectric layer is formed on a second semiconductor substrate. The device layer is bonded onto the dielectric layer.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hsiang Tsai, Chung-Chuan Tseng, Chia-Wei Liu, Li-Hsin Chu
  • Publication number: 20200079753
    Abstract: The present invention provides a compound of formula (I) wherein X, Y, Z1, Z2, R1, R2, A, B, p and q are as disclosed in the specification. A pharmaceutical composition and a method for modulating the Hedgehog pathway are also provided. The present invention further provides a process for preparing the compound.
    Type: Application
    Filed: November 22, 2017
    Publication date: March 12, 2020
    Applicant: DEVELOPMENT CENTER FOR BIOTECHNOLOGY
    Inventors: MANN-YAN KUO, YING-SHUAN LEE, YANN-YU LU, CHIA-WEI LIU, SELINE HSIEH, JU-YING YANG
  • Publication number: 20200052018
    Abstract: A method includes epitaxially growing a first III-V compound layer over a semiconductive substrate. A second III-V compound layer is epitaxially grown over the first III-V compound layer. A source/drain contact is formed over the second III-V compound layer. A gate structure is formed over the second III-V compound layer. A pattern is formed shielding the gate structure and the source/drain contact, in which a portion of the second III-V compound layer is free from coverage by the pattern.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Ying WU, Li-Hsin CHU, Chung-Chuan TSENG, Chia-Wei LIU
  • Patent number: 10553489
    Abstract: A wafer includes a first set of dies and a second set of dies. The wafer further includes a scribe line separating the first set of dies from the second set of dies, wherein the scribe line has a first width. The wafer further includes a plurality of trenches between adjacent dies of the first set of dies and connected to the scribe line, wherein the plurality of trenches has a second width less than the first width, and a depth of each trench of the plurality of trenches is less than a thickness of the wafer.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hsiang Huang, Chung-Chuan Tseng, Chia-Wei Liu, Li Hsin Chu
  • Publication number: 20200035545
    Abstract: A method and structure for providing a semiconductor-on-insulator (SCOI) wafer having a buried low-K dielectric layer includes forming a device layer on a first semiconductor substrate. In various embodiments, at least a portion of the device layer is separated from the first semiconductor substrate, where the separating forms a cleaved surface on the separated portion of the device layer. In some examples, a patterned low-K dielectric layer is formed on a second semiconductor substrate. Thereafter, and in some embodiments, the separated portion of the device layer is bonded, along the cleaved surface, to the patterned low-K dielectric layer.
    Type: Application
    Filed: October 7, 2019
    Publication date: January 30, 2020
    Inventors: Yu-Hsiang TSAI, Chung-Chuan TSENG, Li Hsin CHU, Chia-Wei LIU