Abstract: A cooling motor includes a motor device having a motor casing, a motor assembly arranged in the motor casing, and a centrifugal fan, and a cooling device having first and second cooling components. The first cooling component includes a first cold plate jacket and a first heat circulation pipeline. The first cold plate jacket is sleeved on the motor assembly and thermally connected to a stator, and the first cold plate jacket includes first cold plates. The first thermal circulation pipeline filled with a first working fluid passes through the first cold plate jacket. The second cooling component includes a second cold plate jacket and a second heat circulation pipeline. The second cold plate jacket, sleeving the first cold plate jacket in an insulation manner, includes second cold plates and cooling fins. The second thermal circulation pipeline filled with a second working fluid passes through the second cold plate jacket.

Abstract: A semiconductor device structure and method that utilizes anti-reflection components. The structure includes at least one ramp VIA formed in a VIA isolator layer, at least one anti-reflection component formed on the at least one ramp VIA. A trench isolator layer is formed on the at least one anti-reflection component, and a photoresist is selectively patterned on the trench isolator layer. The trench isolator layer and a portion of the at least one anti-reflection component is etched based upon the selectively patterned photoresist to form a trench metal component hole above the at least one ramp VIA. Thereafter, a trench metal component is formed in the trench metal component hole.

Abstract: An integrated circuit device and a method of manufacturing the same are provided. The method includes steps of: forming a semiconductor device on a substrate; forming a first interconnect structure and a dielectric layer over the semiconductor device; and forming a second interconnect structure over the first interconnect structure, wherein the formation of the second interconnect structure includes: forming an insulating film over the first interconnect structure; depositing an etch stop layer over the insulating film, wherein the etch stop layer and the insulating film include different materials; depositing an isolation layer over the etch stop layer; performing a first etching operation to form a via penetrating the isolation layer and exposing the etch stop layer; and performing a second etching operation to extend the via downward to penetrate the etch stop layer and the insulating film and expose a portion of the first interconnect structure.

Abstract: A damping device is provided. The damping device includes a damper including a mechanical deflector. The damping device includes a post coupled to the mechanical deflector. The damping device includes a case in which the damper is disposed.

Abstract: Apparatuses, methods, and systems for sensor detection may incorporate (i) concealed light sensors including a housing shell and an ambient light sensor positioned to detect light, (ii) a plurality of microvalves with each microvalve including a substrate, a fluid channel through the substrate, a valve element configured to open and close a fluid pathway through the fluid channel, and a piezoresistive material, (iii) a microprocessor that is configured to adjust a charging voltage for a battery, calculated from an output signal, and (iv) a radio frequency transceiver configured to control an antenna tuner to change one or more specified operational parameters of at least one antenna based on an input detected from a set of sensors in a watch body and a set of sensors in a watch band.

Abstract: The disclosed wireless antenna may include a stratified architecture that electrically isolates an antenna radiating element from a ground plane. For example, the disclosed wireless antenna may be included in a wearable device such that the antenna radiating element is capacitively coupled with the bare skin of the wearer. A slot or cleared volume between the antenna radiating element and the ground plane causes electrical fields to close between the antenna radiating element—effectively enlarged by the bare skin of the wearer—and the ground plane. By clearly separating the antenna radiating element and the ground plane and coupling the antenna radiating element to conductive human tissue, the disclosed wireless antenna significantly improves performance at low frequencies such as LTD low bands. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.

Abstract: A damping device is provided. The damping device includes a damper including a mechanical deflector. The damping device includes a post coupled to the mechanical deflector. The damping device includes a case in which the damper is disposed.

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface. A height of the step-height is smaller than a thickness of the first bonding layer.

Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface.

Abstract: Disclosed herein are novel single-stranded anti-sense oligonucleotides (ASOs) capable of reducing the transcription of thioredoxin domain containing protein 5 (TXNDC5) mRNA. Also disclosed is use of the single-stranded ASOs as disclosed herein for manufacturing medicaments suitable for treating a disease associated with upregulation of TXNDC5. Accordingly, a pharmaceutical composition comprising the disclosed ASO molecules is provided; as well as a method of treating a subject suffering from TXNDC5-mediated disease via administering to the subject the disclosed single-stranded ASO molecules.

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

Abstract: Devices and methods of manufacture for a graduated, “step-like,” semiconductor structure having two or more resonator trenches. A semiconductor structure may comprise a first resonator and a second resonator. The first resonator comprising a first metallic resonance layer and a capping plate having a bottom surface that is a first distance from a distal end of the first metallic resonance layer 128. The second resonator comprising a second metallic resonance layer and the capping plate, in which the bottom surface is a second distance from a from a distal end of the second metallic resonance layer 128b, and in which first distance is different from the second distance.

Abstract: A RRAM device is provided. The RRAM device includes: a bottom electrode in a first dielectric layer; a switching layer in a second dielectric layer over the first dielectric layer, wherein a conductive path is formed in the switching layer when a forming voltage is applied; and a needle-like-shaped top electrode region in a third dielectric layer over the second dielectric layer. The needle-like-shaped top electrode region includes: an oxygen-rich dielectric layer, wherein a lower end of the oxygen-rich dielectric layer is a tip; and a top electrode over the oxygen-rich dielectric layer.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.

Abstract: Devices and methods of manufacture for a graduated, “step-like,” capacitance structure having two or more capacitors. A semiconductor structure comprising a capacitor structure, the capacitor structure comprising a first capacitor and a second capacitor. The first capacitor comprising a first bottom electrode and a top electrode having a bottom surface that is a first distance from a top surface of the first bottom electrode. The second capacitor comprising a second bottom electrode and the top electrode, in which the bottom surface is a second distance from a top surface of the second bottom electrode, and in which the first distance is different from the second distance.

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: Devices and methods of manufacture for a graduated, “step-like,” semiconductor structure having two or more resonator trenches. A semiconductor structure may comprise a first resonator and a second resonator. The first resonator comprises a first metallic resonance layer and a capping plate having a bottom surface that is a first distance from a distal end of the first metallic resonance layer. The second resonator comprises a second metallic resonance layer and the capping plate, in which the bottom surface is a second distance from a from a distal end of the second metallic resonance layer, and in which first distance is different from the second distance.