Abstract: Disclosed herein are novel single-stranded anti-sense oligonucleotides (ASOs) capable of reducing the transcription of thioredoxin domain containing protein 5 (TXNDC5) mRNA. Also disclosed is use of the single-stranded ASOs as disclosed herein for manufacturing medicaments suitable for treating a disease associated with upregulation of TXNDC5. Accordingly, a pharmaceutical composition comprising the disclosed ASO molecules is provided; as well as a method of treating a subject suffering from TXNDC5-mediated disease via administering to the subject the disclosed single-stranded ASO molecules.

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

Abstract: A RRAM device is provided. The RRAM device includes: a bottom electrode in a first dielectric layer; a switching layer in a second dielectric layer over the first dielectric layer, wherein a conductive path is formed in the switching layer when a forming voltage is applied; and a needle-like-shaped top electrode region in a third dielectric layer over the second dielectric layer. The needle-like-shaped top electrode region includes: an oxygen-rich dielectric layer, wherein a lower end of the oxygen-rich dielectric layer is a tip; and a top electrode over the oxygen-rich dielectric layer.

Abstract: Devices and methods of manufacture for a graduated, “step-like,” semiconductor structure having two or more resonator trenches. A semiconductor structure may comprise a first resonator and a second resonator. The first resonator comprising a first metallic resonance layer and a capping plate having a bottom surface that is a first distance from a distal end of the first metallic resonance layer 128. The second resonator comprising a second metallic resonance layer and the capping plate, in which the bottom surface is a second distance from a from a distal end of the second metallic resonance layer 128b, and in which first distance is different from the second distance.

Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

Abstract: A power converter is provided. The power converter includes a housing, a heat dissipation module, and a first circuit board. The housing forms a receiving space, wherein the housing includes a first housing port and a second housing port. The heat dissipation module is detachably connected to the housing, and disposed in the receiving space. The heat dissipation module includes an inner path that communicates the first housing port with the second housing port. Working fluid enters the inner path via the first housing port. The working fluid leaves the inner path via the second housing port. The first circuit board includes a first circuit board body and a first heat source, wherein the first heat source is disposed on the first circuit board body, and the first heat source is thermally connected to the inner path of the heat dissipation module.

Abstract: A cooling apparatus is provided. An external cooling fluid flows into an external inlet opening from an external inlet pipe and passes through a heat exchanger to flow out of an external outlet opening to an external outlet pipe. An internal cooling fluid flows into an internal inlet pipe from the server and flows into an internal inlet opening from the internal inlet pipe and passes through the heat exchanger for heat exchange with the external cooling fluid to flow out of an internal outlet opening to an internal outlet pipe. A hot-swap pump has a pump main body, an inlet anti-leakage pipe, an outlet anti-leakage pipe and a hot-swap connector. The inlet anti-leakage pipe includes an inlet connector and an inlet anti-leakage valve. The outlet anti-leakage pipe includes an outlet connector and an outlet anti-leakage valve. The hot-swap connector is electrically connected to the pump main body.

Abstract: A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.

Abstract: Devices and methods of manufacture for a graduated, “step-like,” capacitance structure having two or more capacitors. A semiconductor structure comprising a capacitor structure, the capacitor structure comprising a first capacitor and a second capacitor. The first capacitor comprising a first bottom electrode and a top electrode having a bottom surface that is a first distance from a top surface of the first bottom electrode. The second capacitor comprising a second bottom electrode and the top electrode, in which the bottom surface is a second distance from a top surface of the second bottom electrode, and in which the first distance is different from the second distance.

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: Devices and methods of manufacture for a graduated, “step-like,” semiconductor structure having two or more resonator trenches. A semiconductor structure may comprise a first resonator and a second resonator. The first resonator comprises a first metallic resonance layer and a capping plate having a bottom surface that is a first distance from a distal end of the first metallic resonance layer. The second resonator comprises a second metallic resonance layer and the capping plate, in which the bottom surface is a second distance from a from a distal end of the second metallic resonance layer, and in which first distance is different from the second distance.

Abstract: Interconnect structures and methods of forming interconnect structures are disclosed that provide decreased risk of unwanted via formation through interconnect-level dielectric layers. A method of forming an interconnect structure includes forming first and second dielectric layers over a first metal interconnect feature, where the dielectric layers include localized elevated regions caused by a hillock in the first metal interconnect feature. A planarization process removes the localized elevated region of the second dielectric layer, and third and fourth dielectric layers are formed over the planar upper surface of the second dielectric layer. An etching process through the third and fourth dielectric layers, and into the second dielectric layer, provides a trench having a planar bottom surface.

Abstract: A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.

Abstract: A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.

Abstract: A method of forming a semiconductor structure includes forming a first conductive contact in a first dielectric layer coupled to a first device and forming a second conductive contact in the first dielectric layer coupled to a second device. A first trench is formed in the first dielectric layer having a first depth and exposing at least a portion of the first conductive contact. A second trench is formed in the first dielectric layer having a second depth different than the first depth and exposing at least a portion of the second conductive contact. A first conductive layer is formed in the first trench and the second trench. A second dielectric layer is formed in the first trench and the second trench over the first conductive layer.

Abstract: A cooling motor includes a motor device having a motor casing, a motor assembly arranged in the motor casing, and a centrifugal fan, and a cooling device having first and second cooling components. The first cooling component includes a first cold plate jacket and a first heat circulation pipeline. The first cold plate jacket is sleeved on the motor assembly and thermally connected to a stator, and the first cold plate jacket includes first cold plates. The first thermal circulation pipeline filled with a first working fluid passes through the first cold plate jacket. The second cooling component includes a second cold plate jacket and a second heat circulation pipeline. The second cold plate jacket, sleeving the first cold plate jacket in an insulation manner, includes second cold plates and cooling fins. The second thermal circulation pipeline filled with a second working fluid passes through the second cold plate jacket.