Patents by Inventor Chia-Wei Liu

Chia-Wei Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12261129
    Abstract: A damping device is provided. The damping device includes a damper including a mechanical deflector. The damping device includes a post coupled to the mechanical deflector. The damping device includes a case in which the damper is disposed.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Jheng-Hong Jiang, Shing-Huang Wu, Chia-Wei Liu
  • Publication number: 20250085548
    Abstract: A light field display module including a light field display layer, an adjustment layer, and an image forming layer is provided. The light field display layer is configured to form a light field image beam. The adjustment layer is disposed on a path of the light field image beam, and configured to adjust the light field image beam. The image forming layer is disposed on the path of the light field image beam from the adjustment layer, and configured to change a position of a light field image by changing a direction of the light field image beam. The image forming layer has multiple optical micro-structures.
    Type: Application
    Filed: August 1, 2024
    Publication date: March 13, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Szu-Wei Wu, Yi-Hsiang Huang, Chia-Ping Lin, Yu-Hsiang Liu, Hung Tsou
  • Publication number: 20250081730
    Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.
    Type: Application
    Filed: June 26, 2024
    Publication date: March 6, 2025
    Inventors: Andrew Lin, Alper Ozgurluk, Chao Liang Chien, Cheuk Chi Lo, Chia-Yu Chen, Chien-Chung Wang, Chih Pang Chang, Chih-Hung Yu, Chih-Wei Chang, Chin Wei Hsu, ChinWei Hu, Chun-Kai Tzeng, Chun-Ming Tang, Chun-Yao Huang, Hung-Che Ting, Jung Yen Huang, Lungpao Hsin, Shih Chang Chang, Tien-Pei Chou, Wen Sheng Lo, Yu-Wen Liu, Yung Da Lai
  • Publication number: 20250079363
    Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface. A height of the step-height is smaller than a thickness of the first bonding layer.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Sung Chiang, Chia-Wei Liu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Patent number: 12243839
    Abstract: A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface.
    Type: Grant
    Filed: February 2, 2024
    Date of Patent: March 4, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Sung Chiang, Chia-Wei Liu, Yu-Ruei Chen, Yu-Hsiang Lin
  • Publication number: 20250072294
    Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.
    Type: Application
    Filed: November 14, 2024
    Publication date: February 27, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wei Liu, Jia-Feng Fang, Chun-Hsien Lin
  • Publication number: 20250066793
    Abstract: Disclosed herein are novel single-stranded anti-sense oligonucleotides (ASOs) capable of reducing the transcription of thioredoxin domain containing protein 5 (TXNDC5) mRNA. Also disclosed is use of the single-stranded ASOs as disclosed herein for manufacturing medicaments suitable for treating a disease associated with upregulation of TXNDC5. Accordingly, a pharmaceutical composition comprising the disclosed ASO molecules is provided; as well as a method of treating a subject suffering from TXNDC5-mediated disease via administering to the subject the disclosed single-stranded ASO molecules.
    Type: Application
    Filed: December 28, 2022
    Publication date: February 27, 2025
    Inventors: Ying-Shuan LAILEE, Chia-Wei LIU, Chi-Tang WANG, Pei-Yi TSAI, Chung-Hsiun WU, King LAM, Wei-Ting SUN, Kai-Chien YANG, Hung-Jyun HUANG
  • Patent number: 12239034
    Abstract: A RRAM device is provided. The RRAM device includes: a bottom electrode in a first dielectric layer; a switching layer in a second dielectric layer over the first dielectric layer, wherein a conductive path is formed in the switching layer when a forming voltage is applied; and a needle-like-shaped top electrode region in a third dielectric layer over the second dielectric layer. The needle-like-shaped top electrode region includes: an oxygen-rich dielectric layer, wherein a lower end of the oxygen-rich dielectric layer is a tip; and a top electrode over the oxygen-rich dielectric layer.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jheng-Hong Jiang, Shing-Huang Wu, Chia-Wei Liu
  • Patent number: 12237280
    Abstract: Devices and methods of manufacture for a graduated, “step-like,” semiconductor structure having two or more resonator trenches. A semiconductor structure may comprise a first resonator and a second resonator. The first resonator comprising a first metallic resonance layer and a capping plate having a bottom surface that is a first distance from a distal end of the first metallic resonance layer 128. The second resonator comprising a second metallic resonance layer and the capping plate, in which the bottom surface is a second distance from a from a distal end of the second metallic resonance layer 128b, and in which first distance is different from the second distance.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jheng-Hong Jiang, Shing-Huang Wu, Chia-Wei Liu
  • Publication number: 20250063758
    Abstract: A titanium precursor is used to selectively form a titanium silicide (TiSix) layer in a semiconductor device. A plasma-based deposition operation is performed in which the titanium precursor is provided into an opening, and a reactant gas and a plasma are used to cause silicon to diffuse to a top surface of a transistor structure. The diffusion of silicon results in the formation of a silicon-rich surface of the transistor structure, which increases the selectivity of the titanium silicide formation relative to other materials of the semiconductor device. The titanium precursor reacts with the silicon-rich surface to form the titanium silicide layer. The selective titanium silicide layer formation results in the formation of a titanium silicon nitride (TiSixNy) on the sidewalls in the opening, which enables a conductive structure such as a metal source/drain contact to be formed in the opening without the addition of another barrier layer.
    Type: Application
    Filed: November 5, 2024
    Publication date: February 20, 2025
    Inventors: Cheng-Wei CHANG, Chia-Hung CHU, Hsu-Kai CHANG, Sung-Li WANG, Kuan-Kan HU, Shuen-Shin LIANG, Kao-Feng LIN, Hung Pin LU, Yi-Ying LIU, Chuan-Hui SHEN
  • Publication number: 20250062119
    Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.
    Type: Application
    Filed: November 4, 2024
    Publication date: February 20, 2025
    Inventors: Hung-Te Lin, Chia-Wei Liu, Hung-Chih Yu
  • Patent number: 12224179
    Abstract: The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Sheng Lin, Chi-Jen Liu, Chi-Hsiang Shen, Te-Ming Kung, Chun-Wei Hsu, Chia-Wei Ho, Yang-Chun Cheng, William Weilun Hong, Liang-Guang Chen, Kei-Wei Chen
  • Patent number: 12207451
    Abstract: A power converter is provided. The power converter includes a housing, a heat dissipation module, and a first circuit board. The housing forms a receiving space, wherein the housing includes a first housing port and a second housing port. The heat dissipation module is detachably connected to the housing, and disposed in the receiving space. The heat dissipation module includes an inner path that communicates the first housing port with the second housing port. Working fluid enters the inner path via the first housing port. The working fluid leaves the inner path via the second housing port. The first circuit board includes a first circuit board body and a first heat source, wherein the first heat source is disposed on the first circuit board body, and the first heat source is thermally connected to the inner path of the heat dissipation module.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: January 21, 2025
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Sheng-Nan Tsai, Ying-Chung Chuang, Chia-Jung Liu, Yi-Wei Chen, Han-Yu Tai, Shao-Hsiang Lo
  • Patent number: 12207449
    Abstract: A cooling apparatus is provided. An external cooling fluid flows into an external inlet opening from an external inlet pipe and passes through a heat exchanger to flow out of an external outlet opening to an external outlet pipe. An internal cooling fluid flows into an internal inlet pipe from the server and flows into an internal inlet opening from the internal inlet pipe and passes through the heat exchanger for heat exchange with the external cooling fluid to flow out of an internal outlet opening to an internal outlet pipe. A hot-swap pump has a pump main body, an inlet anti-leakage pipe, an outlet anti-leakage pipe and a hot-swap connector. The inlet anti-leakage pipe includes an inlet connector and an inlet anti-leakage valve. The outlet anti-leakage pipe includes an outlet connector and an outlet anti-leakage valve. The hot-swap connector is electrically connected to the pump main body.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: January 21, 2025
    Assignee: Super Micro Computer, Inc.
    Inventors: Chia-Wei Chen, Te-Chang Lin, Yueh-Ming Liu, Yu-Hsiang Huang, Ya-Lin Liu, Chi-Che Chang
  • Patent number: 12205901
    Abstract: A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jheng-Hong Jiang, Chia-Wei Liu, Shing-Huang Wu
  • Patent number: 12191247
    Abstract: Devices and methods of manufacture for a graduated, “step-like,” capacitance structure having two or more capacitors. A semiconductor structure comprising a capacitor structure, the capacitor structure comprising a first capacitor and a second capacitor. The first capacitor comprising a first bottom electrode and a top electrode having a bottom surface that is a first distance from a top surface of the first bottom electrode. The second capacitor comprising a second bottom electrode and the top electrode, in which the bottom surface is a second distance from a top surface of the second bottom electrode, and in which the first distance is different from the second distance.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: January 7, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jheng-Hong Jiang, Shing-Huang Wu, Chia-Wei Liu
  • Patent number: 12178136
    Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.
    Type: Grant
    Filed: August 28, 2023
    Date of Patent: December 24, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wei Liu, Jia-Feng Fang, Chun-Hsien Lin
  • Patent number: 12165868
    Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Te Lin, Chia-Wei Liu, Hung-Chih Yu
  • Publication number: 20240395739
    Abstract: Devices and methods of manufacture for a graduated, “step-like,” semiconductor structure having two or more resonator trenches. A semiconductor structure may comprise a first resonator and a second resonator. The first resonator comprises a first metallic resonance layer and a capping plate having a bottom surface that is a first distance from a distal end of the first metallic resonance layer. The second resonator comprises a second metallic resonance layer and the capping plate, in which the bottom surface is a second distance from a from a distal end of the second metallic resonance layer, and in which first distance is different from the second distance.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 28, 2024
    Inventors: Jheng-Hong JIANG, Shing-Huang WU, Chia-Wei LIU
  • Patent number: D1064033
    Type: Grant
    Filed: April 29, 2024
    Date of Patent: February 25, 2025
    Assignee: Amazon Technologies, Inc.
    Inventors: Wen-Yo Lu, Matthew J. England, Chia-Song Liu, Tsung-Kai Cheng, Ming-Cheng Cheng, Oleksii Krasnoshchok, Oleksii Shekolian, Sergiy Aafanasov, Mikhail Donskoi, Chia-Wei Chan