Patents by Inventor Chia-Wei Soong

Chia-Wei Soong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11855089
    Abstract: A semiconductor device includes a silicon substrate; a semiconductor fin over the silicon substrate; and an isolation structure over the silicon substrate. The semiconductor fin includes a first portion and a second portion over the first portion. The first portion is surrounded by the isolation structure, and the second portion protrudes above the isolation structure. The second portion has a different crystalline lattice constant than the first portion. The first portion includes a first dopant, and the second portion is substantially free of the first dopant. The semiconductor device further includes a gate structure above the isolation structure and engaging multiple surfaces of the second portion.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Patent number: 11569230
    Abstract: A method for forming a semiconductor device comprises receiving a structure having a substrate, an isolation structure over the substrate, and a fin over the substrate and adjacent to the isolation structure. The method further includes etching a portion of the fin, resulting in a trench, forming a doped material layer over bottom and sidewalls of the trench, and growing at least one epitaxial layer over the doped material layer in the trench. The method further includes recessing the isolation structure and the doped material layer, leaving a first portion of the at least one epitaxial layer surrounded by the doped material layer and performing an annealing process, thereby driving dopants from the doped material layer into the first portion.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Publication number: 20220302113
    Abstract: A semiconductor device includes a silicon substrate; a semiconductor fin over the silicon substrate; and an isolation structure over the silicon substrate. The semiconductor fin includes a first portion and a second portion over the first portion. The first portion is surrounded by the isolation structure, and the second portion protrudes above the isolation structure. The second portion has a different crystalline lattice constant than the first portion. The first portion includes a first dopant, and the second portion is substantially free of the first dopant. The semiconductor device further includes a gate structure above the isolation structure and engaging multiple surfaces of the second portion.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 22, 2022
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Patent number: 11107810
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and the substrate includes a first region and a second region. A gate structure is formed over a fin structure and a first S/D structure has a first volume. A second S/D structure has a second volume, and the second volume is lower than the first volume. A first contact structure is formed over the first S/D structure and a first conductive via is formed over the first contact structure. A power line is formed over the first conductive via, and the power line is electrically connected to the first S/D structure by the first conductive via and the first contact structure.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Pin Tsao, Jeng-Ya Yeh, Chia-Wei Soong
  • Publication number: 20210020634
    Abstract: A method for forming a semiconductor device comprises receiving a structure having a substrate, an isolation structure over the substrate, and a fin over the substrate and adjacent to the isolation structure. The method further includes etching a portion of the fin, resulting in a trench, forming a doped material layer over bottom and sidewalls of the trench, and growing at least one epitaxial layer over the doped material layer in the trench. The method further includes recessing the isolation structure and the doped material layer, leaving a first portion of the at least one epitaxial layer surrounded by the doped material layer and performing an annealing process, thereby driving dopants from the doped material layer into the first portion.
    Type: Application
    Filed: October 5, 2020
    Publication date: January 21, 2021
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Patent number: 10797052
    Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, and a first semiconductor layer over the substrate. At least a portion of the first semiconductor layer is surrounded by the isolation structure. The semiconductor device further includes a doped material layer between the isolation structure and the first semiconductor layer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Publication number: 20200091146
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and the substrate includes a first region and a second region. A gate structure is formed over a fin structure and a first S/D structure has a first volume. A second S/D structure has a second volume, and the second volume is lower than the first volume. A first contact structure is formed over the first S/D structure and a first conductive via is formed over the first contact structure. A power line is formed over the first conductive via, and the power line is electrically connected to the first S/D structure by the first conductive via and the first contact structure.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 19, 2020
    Inventors: Chih-Pin TSAO, Jeng-Ya YEH, Chia-Wei SOONG
  • Patent number: 10276568
    Abstract: In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Sheng Wu, Chen Hua Tsai, Hou-Yu Chen, Chia-Wei Soong, Chih-Pin Tsao
  • Publication number: 20190123049
    Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, and a first semiconductor layer over the substrate. At least a portion of the first semiconductor layer is surrounded by the isolation structure. The semiconductor device further includes a doped material layer between the isolation structure and the first semiconductor layer.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Patent number: 10262878
    Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Jung Liu, Chih-Pin Tsao, Chia-Wei Soong, Jyh-Huei Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20190051542
    Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.
    Type: Application
    Filed: October 9, 2018
    Publication date: February 14, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Jung LIU, Chih-Pin Tsao, Chia-Wei Soong, Jyh-Huei Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 10157924
    Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, and at least one semiconductor layer over the substrate. A first portion of the at least one semiconductor layer is over the isolation structure and a second portion of the at least one semiconductor layer is surrounded by the isolation structure. A doped material layer is between the isolation structure and the second portion of the at least one semiconductor layer.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Patent number: 10109507
    Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Jung Liu, Chih-Pin Tsao, Chia-Wei Soong, Jyh-Huei Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20180190654
    Abstract: In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.
    Type: Application
    Filed: February 27, 2018
    Publication date: July 5, 2018
    Inventors: Yu-Sheng Wu, Chen Hua Tsai, Hou-Yu Chen, Chia-Wei Soong, Chih-Pin Tsao
  • Patent number: 9947658
    Abstract: In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Sheng Wu, Chen Hua Tsai, Hou-Yu Chen, Chia-Wei Soong, Chih-Pin Tsao
  • Publication number: 20170352559
    Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 7, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Jung LIU, Chih-Pin TSAO, Chia-Wei SOONG, Jyh-Huei CHEN, Shu-Hui WANG, Shih-Hsun CHANG
  • Patent number: 9831242
    Abstract: In a method for manufacturing a semiconductor device, a doped layer is formed in a substrate. A barrier layer that is in contact with the doped layer is formed. A semiconductor layer is formed over the substrate and the barrier layer. A fin structure is formed by patterning the semiconductor layer, the barrier layer, and the doped layer such that the fin structure includes a channel region including the semiconductor layer and a well region including the doped layer. An isolation insulating layer is formed such that a first portion of the fin structure protrudes from the isolation insulating layer and a second portion of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over the fin structure and the isolation insulating layer.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wei Soong, Chih-Pin Tsao, Hou-Yu Chen, Chen Hua Tsai
  • Publication number: 20170133371
    Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, and at least one semiconductor layer over the substrate. A first portion of the at least one semiconductor layer is over the isolation structure and a second portion of the at least one semiconductor layer is surrounded by the isolation structure. A doped material layer is between the isolation structure and the second portion of the at least one semiconductor layer.
    Type: Application
    Filed: January 13, 2017
    Publication date: May 11, 2017
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Publication number: 20170125413
    Abstract: In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.
    Type: Application
    Filed: April 11, 2016
    Publication date: May 4, 2017
    Inventors: Yu-Sheng WU, Chen Hua TSAI, Hou-Yu CHEN, Chia-Wei SOONG, Chih-Pin TSAO
  • Publication number: 20170125412
    Abstract: In a method for manufacturing a semiconductor device, a doped layer is formed in a substrate. A barrier layer that is in contact with the doped layer is formed. A semiconductor layer is formed over the substrate and the barrier layer. A fin structure is formed by patterning the semiconductor layer, the barrier layer, and the doped layer such that the fin structure includes a channel region including the semiconductor layer and a well region including the doped layer. An isolation insulating layer is formed such that a first portion of the fin structure protrudes from the isolation insulating layer and a second portion of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over the fin structure and the isolation insulating layer.
    Type: Application
    Filed: April 1, 2016
    Publication date: May 4, 2017
    Inventors: Chia-Wei SOONG, Chih-Pin TSAO, Hou-Yu CHEN, Chen Hua TSAI