Patents by Inventor Chia-Wei Tseng
Chia-Wei Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966546Abstract: A display device includes a base layer, a touch sensing layer, a light guide module and a display panel. The touch sensing layer is disposed on the base layer. The light guide module is disposed on the touch sensing layer. The touch sensing layer is located between the light guide module and the display panel, and the touch sensing layer and one of the light guide module and the display panel have no adhesive material therebetween.Type: GrantFiled: August 19, 2021Date of Patent: April 23, 2024Assignee: E Ink Holdings Inc.Inventors: Chen-Cheng Lin, Chia-I Liu, Kun-Hsien Lee, Hung-Wei Tseng
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Publication number: 20240128143Abstract: Provided are a package structure and a method of forming the same. The method includes: forming an interconnect structure on a substrate; performing a laser grooving process to form a first opening in the interconnect structure and form a debris layer on a sidewall of the first opening in a same step; forming a protective layer to fill in the first opening and cover the debris layer and the interconnect structure; patterning the protective layer to form a second opening, wherein the second opening is spaced from the debris layer by the protective layer; performing a planarization process on the protective layer to expose a topmost contact pad of the interconnect structure; and performing a mechanical dicing process through the second opening to form a third opening in the substrate and cut the substrate into a plurality of semiconductor dies.Type: ApplicationFiled: February 1, 2023Publication date: April 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Han Hsieh, Yu-Jin Hu, Hua-Wei Tseng, An-Jhih Su, Der-Chyang Yeh
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Patent number: 11956563Abstract: A method for identifying video signal source is provided. The method includes the following steps. A first identification code is assigned to a first transmitter device by a receiver control unit of a receiver device. A first video data is transmitted by the first transmitter device. The first video data and a first identification image corresponding to the first identification code are combined as a first combined video data by the receiver control unit. The first combined video data is outputted to a display device by the receiver control unit.Type: GrantFiled: January 7, 2021Date of Patent: April 9, 2024Assignee: BenQ CorporationInventors: Chia-Nan Shih, Chen-Chi Wu, Lin-Yuan You, Chin-Fu Chiang, Ron-Kun Tseng, Chuang-Wei Wu
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Patent number: 11933809Abstract: The present application discloses an inertial sensor comprising a proof mass, an anchor, a flexible member and several sensing electrodes. The anchor is positioned on one side of the sensing, mass block in a first axis. The flexible member is connected to the anchor point and extends along the first axis towards the proof mass to connect the proof mass, in which the several sensing electrodes are provided. In this way, the present application can effectively solve the problems of high difficulty in the production and assembly of inertial sensors and poor product reliability thereof.Type: GrantFiled: April 6, 2022Date of Patent: March 19, 2024Assignee: SENSORTEK TECHNOLOGY CORP.Inventors: Shih-Wei Lee, Chia-Hao Lin, Shih-Hsiung Tseng, Kuan-Ju Tseng, Chao-Shiun Wang
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Patent number: 11907633Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.Type: GrantFiled: August 9, 2022Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
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Publication number: 20230251531Abstract: A display device includes a substrate, a transistor, a pixel electrode, a first conductive layer and a second conductive layer. The transistor is disposed on the substrate. The pixel electrode is disposed on the substrate. The pixel electrode is electrically connected to the transistor. The first conductive layer is disposed on the pixel electrode. The first conductive layer has a first slit. The second conductive layer is disposed on the pixel electrode. The second conductive layer has a second slit. The first slit and the second slit are overlapped with the pixel electrode.Type: ApplicationFiled: April 7, 2023Publication date: August 10, 2023Applicant: Innolux CorporationInventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
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Patent number: 11656508Abstract: A display device, including a substrate, a first transistor, a second transistor, a first pixel electrode, a second pixel electrode, and a common electrode layer, is provided. The first transistor and the second transistor are disposed on the substrate. The first pixel electrode is electrically connected to the first transistor. The second pixel electrode is electrically connected to the second transistor. The second pixel electrode is disposed adjacent to the first pixel electrode. The common electrode layer has a first slit. The first slit spans from the first pixel electrode to the second pixel electrode.Type: GrantFiled: January 12, 2022Date of Patent: May 23, 2023Assignee: Innolux CorporationInventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
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Publication number: 20220382948Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
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Patent number: 11494543Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.Type: GrantFiled: May 26, 2020Date of Patent: November 8, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
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Publication number: 20220252948Abstract: A display device, including a substrate, a first transistor, a second transistor, a first pixel electrode, a second pixel electrode, and a common electrode layer, is provided. The first transistor and the second transistor are disposed on the substrate. The first pixel electrode is electrically connected to the first transistor. The second pixel electrode is electrically connected to the second transistor. The second pixel electrode is disposed adjacent to the first pixel electrode. The common electrode layer has a first slit. The first slit spans from the first pixel electrode to the second pixel electrode.Type: ApplicationFiled: January 12, 2022Publication date: August 11, 2022Applicant: Innolux CorporationInventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
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Patent number: 10812505Abstract: A computer system includes an openflow switch, configured to receive a plurality of packets; a network controller, coupled to the openflow switch and configured to determine a route of each of the plurality of packets; and a detecting and defending system, configured to perform transformation of information formats of the plurality of packets, retrieve and label the plurality of packets to determine whether the plurality of packets are abnormal or not and generate a defending determination.Type: GrantFiled: December 12, 2018Date of Patent: October 20, 2020Assignee: National Chung-Shan Institute of Science and TechnologyInventors: Li-Der Chou, Chia-Wei Tseng, Chia-Kuan Yen, Wei-Hsiang Tsai, Tsung-Fu Ou, Yi-Hsuan Chiu, Wei-Yu Chen, Meng-Sheng Lai
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Publication number: 20200285797Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.Type: ApplicationFiled: May 26, 2020Publication date: September 10, 2020Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
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Publication number: 20200195661Abstract: A computer system includes an openflow switch, configured to receive a plurality of packets; a network controller, coupled to the openflow switch and configured to determine a route of each of the plurality of packets; and a detecting and defending system, configured to perform transformation of information formats of the plurality of packets, retrieve and label the plurality of packets to determine whether the plurality of packets are abnormal or not and generate a defending determination.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: Li-Der Chou, Chia-Wei Tseng, Chia-Kuan Yen, Wei-Hsiang Tsai, Tsung-Fu Ou, Yi-Hsuan Chiu, Wei-Yu Chen, Meng-Sheng Lai
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Patent number: 10685162Abstract: A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.Type: GrantFiled: December 20, 2018Date of Patent: June 16, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
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Publication number: 20190121931Abstract: A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.Type: ApplicationFiled: December 20, 2018Publication date: April 25, 2019Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
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Patent number: 10163883Abstract: A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across the boundary of the first layout device and the second layout device; and disposing a cut layer on the conductive path and nearby the boundary. The first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.Type: GrantFiled: June 15, 2016Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
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Publication number: 20170365592Abstract: A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across the boundary of the first layout device and the second layout device; and disposing a cut layer on the conductive path and nearby the boundary. The first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.Type: ApplicationFiled: June 15, 2016Publication date: December 21, 2017Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
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Publication number: 20130076630Abstract: A method and a computer system for keystroke event notification are provided. The method includes a number of steps. A keyboard controller scans a number of keys contained in a keyboard. The keys include at least one pressure-sensitive key and at least two key-functions are assigned to each of the at least one pressure-sensitive key in response to a pressure applied on the pressure-sensitive key. When one of the pressure-sensitive keys is scanned by the keyboard controller, the keyboard controller measures the pressure applied on the pressure-sensitive key. The keyboard controller uses at least two pressure thresholds to determine a level of the measured pressure. The keyboard controller controls a storage device containing a source code of a basic input/output system (BIOS) to deliver a keystroke event on the basis of the determination result, so as to activate one of the key-functions of the pressure-sensitive key.Type: ApplicationFiled: February 10, 2012Publication date: March 28, 2013Applicant: WISTRON CORPORATIONInventors: Chia-Wei Tseng, Kuan-Yu Kao