Patents by Inventor Chia-Wei Tseng

Chia-Wei Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240369885
    Abstract: A display device includes a substrate, a semiconductor, an electrode, a first conductive layer and a second conductive layer. The semiconductor is disposed on the substrate. The electrode is disposed on the substrate. The electrode is electrically connected to the semiconductor. The first conductive layer is overlapped with the electrode. The first conductive layer has a first opening. The second conductive layer is overlapped with the electrode. The second conductive layer has a second opening. The second conductive layer is closer to the substrate than the first conductive layer, and an area of the second opening is greater than an area of the first opening.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Applicant: Innolux Corporation
    Inventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
  • Patent number: 12072587
    Abstract: A display device includes a substrate, a transistor, a pixel electrode, a first conductive layer and a second conductive layer. The transistor is disposed on the substrate. The pixel electrode is disposed on the substrate. The pixel electrode is electrically connected to the transistor. The first conductive layer is disposed on the pixel electrode. The first conductive layer has a first slit. The second conductive layer is disposed on the pixel electrode. The second conductive layer has a second slit. The first slit and the second slit are overlapped with the pixel electrode.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: August 27, 2024
    Assignee: Innolux Corporation
    Inventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
  • Patent number: 11907633
    Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Publication number: 20230251531
    Abstract: A display device includes a substrate, a transistor, a pixel electrode, a first conductive layer and a second conductive layer. The transistor is disposed on the substrate. The pixel electrode is disposed on the substrate. The pixel electrode is electrically connected to the transistor. The first conductive layer is disposed on the pixel electrode. The first conductive layer has a first slit. The second conductive layer is disposed on the pixel electrode. The second conductive layer has a second slit. The first slit and the second slit are overlapped with the pixel electrode.
    Type: Application
    Filed: April 7, 2023
    Publication date: August 10, 2023
    Applicant: Innolux Corporation
    Inventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
  • Patent number: 11656508
    Abstract: A display device, including a substrate, a first transistor, a second transistor, a first pixel electrode, a second pixel electrode, and a common electrode layer, is provided. The first transistor and the second transistor are disposed on the substrate. The first pixel electrode is electrically connected to the first transistor. The second pixel electrode is electrically connected to the second transistor. The second pixel electrode is disposed adjacent to the first pixel electrode. The common electrode layer has a first slit. The first slit spans from the first pixel electrode to the second pixel electrode.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: May 23, 2023
    Assignee: Innolux Corporation
    Inventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
  • Publication number: 20220382948
    Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
  • Patent number: 11494543
    Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Publication number: 20220252948
    Abstract: A display device, including a substrate, a first transistor, a second transistor, a first pixel electrode, a second pixel electrode, and a common electrode layer, is provided. The first transistor and the second transistor are disposed on the substrate. The first pixel electrode is electrically connected to the first transistor. The second pixel electrode is electrically connected to the second transistor. The second pixel electrode is disposed adjacent to the first pixel electrode. The common electrode layer has a first slit. The first slit spans from the first pixel electrode to the second pixel electrode.
    Type: Application
    Filed: January 12, 2022
    Publication date: August 11, 2022
    Applicant: Innolux Corporation
    Inventors: Feng-Ching Lin, Chia-Wei Tseng, Wen-Ming Hung, Shu-Hui Chang
  • Patent number: 10812505
    Abstract: A computer system includes an openflow switch, configured to receive a plurality of packets; a network controller, coupled to the openflow switch and configured to determine a route of each of the plurality of packets; and a detecting and defending system, configured to perform transformation of information formats of the plurality of packets, retrieve and label the plurality of packets to determine whether the plurality of packets are abnormal or not and generate a defending determination.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 20, 2020
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Li-Der Chou, Chia-Wei Tseng, Chia-Kuan Yen, Wei-Hsiang Tsai, Tsung-Fu Ou, Yi-Hsuan Chiu, Wei-Yu Chen, Meng-Sheng Lai
  • Publication number: 20200285797
    Abstract: A layout method comprises selecting a first and a second layout devices in a layout of an integrated circuit. The second layout device abuts the first layout device at a boundary therebetween. The layout method also comprises disposing a first and a second conductive paths across the boundary, and respectively disposing a first and a second cut layers on the first and second conductive paths nearby the boundary. The layout method also comprises disconnecting the first layout device from the second layout device by cutting the first conductive path into two conductive portions according to a first position of the first cut layer and cutting the second conductive path into two conductive portions a second position of the second cut layer. The layout method also comprises moving the first cut layer to align with the second cut layer.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
  • Publication number: 20200195661
    Abstract: A computer system includes an openflow switch, configured to receive a plurality of packets; a network controller, coupled to the openflow switch and configured to determine a route of each of the plurality of packets; and a detecting and defending system, configured to perform transformation of information formats of the plurality of packets, retrieve and label the plurality of packets to determine whether the plurality of packets are abnormal or not and generate a defending determination.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Li-Der Chou, Chia-Wei Tseng, Chia-Kuan Yen, Wei-Hsiang Tsai, Tsung-Fu Ou, Yi-Hsuan Chiu, Wei-Yu Chen, Meng-Sheng Lai
  • Patent number: 10685162
    Abstract: A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Publication number: 20190121931
    Abstract: A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
  • Patent number: 10163883
    Abstract: A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across the boundary of the first layout device and the second layout device; and disposing a cut layer on the conductive path and nearby the boundary. The first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Cheok-Kei Lei, Yu-Chi Li, Chia-Wei Tseng, Zhe-Wei Jiang, Chi-Lin Liu, Jerry Chang-Jui Kao, Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang
  • Publication number: 20170365592
    Abstract: A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across the boundary of the first layout device and the second layout device; and disposing a cut layer on the conductive path and nearby the boundary. The first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
    Type: Application
    Filed: June 15, 2016
    Publication date: December 21, 2017
    Inventors: CHEOK-KEI LEI, YU-CHI LI, CHIA-WEI TSENG, ZHE-WEI JIANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, JUNG-CHAN YANG, CHI-YU LU, HUI-ZHONG ZHUANG
  • Publication number: 20130076630
    Abstract: A method and a computer system for keystroke event notification are provided. The method includes a number of steps. A keyboard controller scans a number of keys contained in a keyboard. The keys include at least one pressure-sensitive key and at least two key-functions are assigned to each of the at least one pressure-sensitive key in response to a pressure applied on the pressure-sensitive key. When one of the pressure-sensitive keys is scanned by the keyboard controller, the keyboard controller measures the pressure applied on the pressure-sensitive key. The keyboard controller uses at least two pressure thresholds to determine a level of the measured pressure. The keyboard controller controls a storage device containing a source code of a basic input/output system (BIOS) to deliver a keystroke event on the basis of the determination result, so as to activate one of the key-functions of the pressure-sensitive key.
    Type: Application
    Filed: February 10, 2012
    Publication date: March 28, 2013
    Applicant: WISTRON CORPORATION
    Inventors: Chia-Wei Tseng, Kuan-Yu Kao