Patents by Inventor Chia-Wei Wang

Chia-Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190315835
    Abstract: The present invention relates to compositions comprising factor VIII coagulation factors linked to extended recombinant polypeptide (XTEN), isolated nucleic acids encoding the compositions and vectors and host cells containing the same, and methods of making and using such compositions in treatment of factor VIII-related diseases, disorders, and conditions.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 17, 2019
    Inventors: Volker SCHELLENBERGER, Pei-Yun CHANG, Fatbardha VARFAJ, John KULMAN, Tongyao LIU, Garabet G. TOBY, Haiyan JIANG, Robert PETERS, Deping WANG, Baisong MEI, Joshua SILVERMAN, Chia-Wei WANG, Benjamin SPINK, Nathan GEETHING
  • Patent number: 10421798
    Abstract: The present invention relates to compositions comprising factor VIII coagulation factors linked to extended recombinant polypeptide (XTEN), isolated nucleic acids encoding the compositions and vectors and host cells containing the same, and methods of making and using such compositions in treatment of factor VIII-related diseases, disorders, and conditions.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: September 24, 2019
    Assignee: BIOVERATIV THERAPEUTICS INC.
    Inventors: Volker Schellenberger, Pei-Yun Chang, Fatbardha Varfaj, Sheng Ding, Joshua Silverman, Chia-wei Wang, Benjamin Spink, Willem P. Stemmer, Volker Schellenberger, Nathan Geething, John Kulman, Tongyao Liu, Garabet G. Toby, Haiyan Jiang, Robert Peters, Deping Wang, Baisong Mei
  • Patent number: 10332574
    Abstract: An embedded memory includes a memory interface circuit, a cell array, and a peripheral circuit. The memory interface circuit receives at least a clock signal, a non-clock signal, and a setup-hold time control setting, and includes a programmable path delay circuit that is used to set a path delay of at least one of a clock path and a non-clock path according to the setup-hold time control setting. The clock path is used to deliver the clock signal, and the non-clock path is used to deliver the non-clock signal. The peripheral circuit is used to access the cell array according to at least the clock signal provided from the clock path and the non-clock signal.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 25, 2019
    Assignee: MEDIATEK INC.
    Inventor: Chia-Wei Wang
  • Publication number: 20190153115
    Abstract: The present invention relates to bispecific chimeric polypeptide assembly compositions comprising bulking moieties linked to binding domains by cleavable release segments that, when cleaved are capable of concurrently binding effector T cells with targeted tumor or cancer cells and effecting cytolysis of the tumor cells or cancer cells. The invention also provides compositions and methods of making and using the cleavable chimeric polypeptide assembly compositions.
    Type: Application
    Filed: August 26, 2016
    Publication date: May 23, 2019
    Inventors: Volker SCHELLENBERGER, Fan YANG, Desiree THAYER, Bee-Cheng SIM, Chia-Wei WANG
  • Publication number: 20190108890
    Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.
    Type: Application
    Filed: December 6, 2018
    Publication date: April 11, 2019
    Inventors: Chia-Wei Wang, Shu-Lin Lai, Yi-Te Chiu
  • Publication number: 20190088990
    Abstract: Disclosed are systems that include a plurality of solid state rechargeable battery cells. The system can be configured to power a drivetrain and can include a rolled substrate and at least one electrochemical cell overlying the surface region of the rolled substrate. The electrochemical cell can include a positive electrode, a solid state layer, a negative electrode, and an electrically conductive material.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Applicant: Dyson Technology Limited
    Inventors: Ann Marie SASTRY, Chia-Wei WANG, Yen-Hung CHEN, HyonCheol KIM, Xiangchun ZHANG, Myoungdo CHUNG
  • Publication number: 20190088978
    Abstract: A method for the continuous or semi-batch manufacture of a solid-state battery device using a high speed process. The method can include forming multiple repeating stacks of thin film layers overlying a substrate in order to form multiple solid state batteries connected in series or parallel, wherein forming the multiple repeating stacks of thin film layers includes forming a polymer interlayer. The method can also include stacking multiple stacks of thin film layers of multi-layer battery cells connected in parallel or in series.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Applicant: Dyson Technology Limited
    Inventors: Marc LANGLOIS, Chia-Wei WANG, Ann Marie SASTRY, HyonCheol KIM, Myoungdo CHUNG, Xiangchun ZHANG, Yen-Hung CHEN
  • Publication number: 20190089023
    Abstract: An integrated energy storage system can include a first, second, and third energy storage units and a controller. The first energy storage units can have a gravimetric energy density of greater than 180 Wh/kg and volumetric energy density greater than 450 Wh/L in an environmental temperature above 0° C., the second energy storage units can have a gravimetric power density of greater than 450 W/kg and volumetric power density greater than 1080 W/L in an environmental temperature above 0° C., and the third energy storage units can be configured to operate in an environmental temperature as low as ?100° C. The controller can be programmed to receive inputs from voltage sensors, current sensors, and temperature sensors, and to allocate the current or power among the first, second, or third energy storage units depending on a power consumption from an application load and an environmental temperature.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Applicant: Dyson Technology Limited
    Inventors: Ann Marie SASTRY, Chia-Wei WANG, Yen-Hung CHEN, Xiangchun ZHANG, HyonCheol KIM, Myoungdo CHUNG
  • Publication number: 20190083577
    Abstract: The present invention relates to extended recombinant polypeptide (XTEN) compositions, conjugate compositions comprising XTEN and XTEN linked to cross-linkers useful for conjugation to pharmacologically active payloads, methods of making highly purified XTEN, methods of making XTEN-linker and XTEN-payload conjugates, and methods of using the XTEN-cross-linker and XTEN-payload compositions.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 21, 2019
    Inventors: Volker Schellenberger, Vladimir Podust, Chia-Wei Wang, Bryant MCLAUGHLIN, Bee-Cheng Sim, Sheng Ding, Chen Gu
  • Publication number: 20190088924
    Abstract: A high speed deposition apparatus for the manufacture of solid state batteries. The apparatus can be used for the manufacture of solid state multilayer stacked battery devices via a vacuum deposition process. In various embodiments, the manufacturing apparatus can include a containment vessel, a reactor region, a process region, a work piece, one or more vacuum chambers, and an energy source. A complete stack of battery layers can be manufactured in a single vacuum cycle, having background gas, pressure, and deposition rate optimized and controlled for the deposition of each layer. The work piece can include a drum and a substrate, which can be a commercial polymer or metallic web, that are temperature controlled. Masks can be used to delineate or shape layers within the multi-layer stacked electrochemical device manufactured by embodiments of the apparatus.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Applicant: Dyson Technology Limited
    Inventors: Chia-Wei WANG, Yen-Hung CHEN, HyonCheol KIM, Marc LANGLOIS, Myoungdo CHUNG, Ann Marie SASTRY, Xiangchun ZHANG
  • Publication number: 20190088923
    Abstract: A method of producing a monolithically integrated high energy density solid-state battery device. The method can include positioning a substrate and depositing one or more stacked monolithically integrated high energy density solid-state electrochemical cells in series or in parallel configurations sequentially or individually. Each of these cells can have a first barrier layer, a cathode current collector deposited overlying the first barrier layer, a cathode overlying the electrically conductive layer, an anode, an anode current collector deposited overlying the solid state layer of negative electrode material, and a second barrier layer.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Applicant: Dyson Technology Limited
    Inventors: Ann Marie SASTRY, Chia-Wei WANG, Yen-Hung CHEN, Xiangchun ZHANG, HyonCheol KIM, Myoungdo CHUNG
  • Publication number: 20190088954
    Abstract: A pulsed laser can be used to ablate the desired thin film layers at a desired location, to a desired depth, without impinging significantly upon other layers. The battery cell layer order may be optionally optimized to aid in ease of laser ablation. The laser process can isolate layers of thin film within sufficient proximity to at least one edge of the final thin film battery stack to optimize active battery area.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Applicant: Dyson Technology Limited
    Inventors: Thomas V. WEIGMAN, Svetlana LUKICH, Ann Marie SASTRY, Chia-Wei WANG, Yen-Hung CHEN, Xiangchun ZHANG, HyonCheol KIM, Myoungdo CHUNG
  • Publication number: 20190088996
    Abstract: A multi-layered solid-state battery device can have a substrate member having a surface region and a thin film battery device layer overlying the barrier material. The thin film battery device layer can comprise a cathode current collector, a cathode device, an electrolyte, an anode device, and an anode current collector. The device can have a non-planar surface region configured from the thin film battery device and a first polymer material overlying the thin film battery device and configured to fill in a gap region of the non-planar surface region and a planarizing surface region configured from the first polymer material.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Applicant: Dyson Technology Limited
    Inventors: Ann Marie SASTRY, Chia-Wei WANG, Yen-Hung CHEN, HyonCheol KIM, Xiangchun ZHANG, Myoungdo CHUNG
  • Publication number: 20190074054
    Abstract: A data line control circuit has a data line driving circuit and a write-assist data line driving circuit. The data line driving circuit is used to drive differential data lines during a write operation of at least one memory cell. The write-assist data line driving circuit is used to drive at least one write-assist data line during the write operation of the at least one memory cell, wherein the at least one write-assist data line is isolated from the differential data lines, and is driven to have a first voltage transition from a first voltage level to a second voltage level, such that one of the differential data lines has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling.
    Type: Application
    Filed: June 26, 2018
    Publication date: March 7, 2019
    Inventors: Chia-Wei Wang, Yi-Te Chiu, Wen-Pin Hsieh
  • Patent number: 10181358
    Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: January 15, 2019
    Assignee: MEDIATEK INC.
    Inventors: Chia-Wei Wang, Shu-Lin Lai, Yi-Te Chiu
  • Patent number: 10172953
    Abstract: The present invention relates to extended recombinant polypeptide (XTEN) compositions, conjugate compositions comprising XTEN and XTEN linked to cross-linkers useful for conjugation to pharmacologically active payloads, methods of making highly purified XTEN, methods of making XTEN-linker and XTEN-payload conjugates, and methods of using the XTEN-cross-linker and XTEN-payload compositions.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: January 8, 2019
    Assignee: Amunix Operating Inc.
    Inventors: Volker Schellenberger, Vladimir Podust, Chia-Wei Wang, Bryant McLaughlin, Bee-Cheng Sim, Sheng Ding, Chen Gu
  • Publication number: 20180346952
    Abstract: The present invention relates to binding fusion protein compositions comprising targeting moieties linked to extended recombinant polypeptide (XTEN), binding fusion protein-drug conjugate compositions, and XTEN-drug conjugate compositions, isolated nucleic acids encoding the compositions and vectors and host cells containing the same, and methods of using such compositions in treatment of diseases, disorders, and conditions.
    Type: Application
    Filed: April 17, 2018
    Publication date: December 6, 2018
    Inventors: Volker Schellenberger, Joshua Silverman, Chia-wei Wang, Benjamin Spink, Willem P.C Stemmer, Nathan C. Geething
  • Publication number: 20180277179
    Abstract: An embedded memory includes a memory interface circuit, a cell array, and a peripheral circuit. The memory interface circuit receives at least a clock signal, a non-clock signal, and a setup-hold time control setting, and includes a programmable path delay circuit that is used to set a path delay of at least one of a clock path and a non-clock path according to the setup-hold time control setting. The clock path is used to deliver the clock signal, and the non-clock path is used to deliver the non-clock signal. The peripheral circuit is used to access the cell array according to at least the clock signal provided from the clock path and the non-clock signal.
    Type: Application
    Filed: November 21, 2017
    Publication date: September 27, 2018
    Inventor: Chia-Wei Wang
  • Publication number: 20180244736
    Abstract: The present invention relates to compositions comprising biologically active proteins linked to extended recombinant polypeptide (XTEN), isolated nucleic acids encoding the compositions and vectors and host cells containing the same, and methods of using such compositions in treatment of glucose-related diseases, metabolic diseases, coagulation disorders, and growth hormone-related disorders and conditions.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 30, 2018
    Inventors: Volker Schellenberger, Joshua Silverman, Chia-wei Wang, Benjamin Spink, Willem P. Stemmer, Nathan Geething, Wayne To, Jeffrey L. Cleland
  • Patent number: 10000543
    Abstract: The present invention relates to compositions comprising glucose regulating peptides linked to extended recombinant polypeptide (XTEN), isolated nucleic acids encoding the compositions and vectors and host cells containing the same, and methods of making and using such compositions in treatment of glucose regulating peptide-related diseases, disorders, and conditions.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 19, 2018
    Assignee: Amunix Operating Inc.
    Inventors: Volker Schellenberger, Joshua Silverman, Willem P. Stemmer, Chia-wei Wang, Nathan Geething, Jeffrey L. Cleland