Abstract: An image processing system includes: a first image processing device for performing a first image enhancement process on a source image to generate a first enhanced image; one or more second images processing device, each of which is used to perform a second image enhancement processing on a size-reduced image generated based on the source image, and accordingly to output one or more second enhanced images whose size identical to the source image; and an output controller for analyzing regional frequency characteristics of the source image to generate an analysis result, determining one or more region weights according to the analysis result, and synthesize the first enhanced image with the one or more second enhanced images according to the one or more region weights, thereby to generate an output image.

Abstract: A compensation circuit is applied to a successive-approximation register (SAR) analog-to-digital converter (ADC) (SAR ADC) that includes a comparator, and the comparator includes a first transistor and a second transistor. The first transistor and the second transistor receive an input signal during a sampling phase, and the comparator determines at least one bit of a digital output code during a comparison phase. The compensation circuit includes a voltage generator coupled to the comparator for providing a first voltage to a first bulk of the first transistor and a second bulk of the second transistor during the sampling phase and providing a second voltage to the first bulk of the first transistor and the second bulk of the second transistor during the comparison phase.

Abstract: An image processor circuit includes a first processor circuit and a second processor circuit. In a two-pixel mode, the first processor circuit is configured to process a first part of first input data and the second processor circuit is configured to process a second part of the first input data to generate output data for a display panel to display. In a picture-in-picture mode, the first processor circuit is configured to process second input data to generate main-picture output data and the second processor circuit is configured to process third input data to generate sub-picture output data for the display panel to display.

Abstract: An image processor circuit includes a first processor circuit and a second processor circuit. In a two-pixel mode, the first processor circuit is configured to process a first part of first input data and the second processor circuit is configured to process a second part of the first input data to generate output data for a display panel to display. The first input data includes K columns, the first part includes 1st to Mth columns of the first input data, and the second part includes Nth to Kth columns of the first input data. N is less than K/2 and M is greater than K/2.

Abstract: A system is adapted to perform an image processing method. The processing method includes: obtaining input image data, a first training result, a second training result, and an interpolation lookup table; segmenting the input image data into a plurality of feature blocks according to a total quantity of area interpolations; establishing a position mapping relationship to record the feature blocks corresponding to positions of all of the area interpolations; assigning corresponding area interpolations to the feature blocks according to the position mapping relationship; obtaining an interpolation parameter for each of the feature blocks according to the first training result, the second training result, and the area interpolation; performing block convolution on each of the interpolation parameters and the corresponding feature block to obtain an output feature result; and obtaining an output image by combining the output feature results according to the position mapping relationship.

Abstract: A super resolution (SR) image generating device includes a receiving circuit, a first configurable basic block pool circuit, a first shuffle circuit, a second configurable basic block pool circuit, and a second shuffle circuit. The receiving circuit is arranged to receive an input image. The first configurable basic block pool circuit is arranged to configure multiple first basic blocks according to the input image for performing convolution operations, to generate multiple first operation results. The first shuffle circuit is arranged to shuffle the multiple first operation results to generate a first SR output image. The second configurable basic block pool circuit is arranged to configure multiple second basic blocks according to the input image for performing convolution operations, to generate multiple second operation results. The second shuffle circuit is arranged to shuffle the multiple second operation results to generate a second SR output image.

Abstract: A latch includes at least one first standard cell logic gate and at least one second standard cell logic gate. The first standard cell logic gate includes a first input terminal, a second input terminal, a third input terminal, and a first output terminal. The second standard cell logic gate includes a fourth input terminal, a fifth input terminal, a sixth input terminal, and a second output terminal. The first input terminal and the second input terminal receive a first input signal. The third input terminal receives a first output signal. The first output terminal outputs a second output signal. The fourth input terminal receives the second output signal. The fifth input terminal and the sixth input terminal receive a second input signal. The second output terminal outputs the first output signal.

Abstract: A super resolution image generating device capable of processing an image flexibly includes a scaling-up circuit, a front-end circuit, a first branch circuit, a second branch circuit, and an arithmetic circuit. The scaling-up circuit scales up the image to generate an enlarged image including N pixel values. The front-end circuit extracts features of the image to generate a front-end feature map. The first branch circuit extracts features of the front-end feature map to generate a first feature map, and scales up the first feature map to generate N first values. The second branch circuit processes the front-end feature map to generate a second feature map, scales up the second feature map to generate N second values, and processes the N second values to generate N processed values. The arithmetic circuit combines the N pixel values, the N first values, and the N processed values to generate a super resolution image.

Abstract: An image display system includes a display device, a second memory circuit, and an image processor circuit. The display device includes a panel and a first memory circuit, in which the first memory circuit is configured to store first predetermined data for controlling the panel. The second memory circuit is configured to store second predetermined data. The image processor circuit is configured to read first part data in the first predetermined data and second part data in the second predetermined data and compare the first part data with the second part data. If the first part data is identical to the second part data, the image processor circuit is further configured to output a driving signal according to the second predetermined data to control the panel to start displaying an image.

Abstract: An audiovisual system with a shared image-processing procedure and a method for processing video therein are provided. The audiovisual system performs the image-processing procedure on a specific format video for optimizing images of the video. If a video format is not supported by the image-processing procedure in the audiovisual system, the video is converted to a video format supported by the audiovisual system. Various videos of different formats can accordingly share the same image-processing procedure. In the method, a first format conversion procedure is performed for converting a received second format video to a first format video that is supported by the image-processing procedure performed in the audiovisual system. The first format video can then be processed by the audiovisual system. It is determined if one more format conversion is required according to the format supported by a display at an output end of the audiovisual system.

Abstract: A method for processing a video with a dynamic video-based super-resolution network and a circuit system are provided. In the method, quality scores used to assess a quality of an input video are calculated based on image features of the input video. A moving average algorithm is performed on the quality scores of multiple frames of the input video for obtaining a moving average score. Two corresponding weight tables are selected according to the moving average score. The two weight tables are used to calculate a blending weight that is applied to a neural network super-resolution algorithm. The blending weight is applied to the neural network super-resolution algorithm, so as to produce an output video.

Abstract: A super resolution (SR) image generation circuit includes an image scale-up circuit, a stable SR processing circuit, a generative adversarial network (GAN) processing circuit, and a configurable basic block pool circuit. The image scale-up circuit is arranged to receive and process an input image to generate a scaled-up image. The stable SR processing circuit is arranged to receive a feature map of the input image to generate a stable delta value. The GAN processing circuit is arranged to receive the feature map to generate a GAN delta value. The configurable basic block pool circuit is arranged to dynamically configure a plurality of basic blocks according to a depth requirement of the input image, to generate a configuration result. The SR image generation circuit generates an SR image according to the scaled-up image, the stable delta value, and the GAN delta value.

Abstract: An image processing circuit includes a receiving circuit, a transmitting circuit, a first asynchronous handshake circuit, a super resolution scale-up model and a second asynchronous handshake circuit. The receiving circuit is arranged to receive an input image with a first pixel clock frequency. The first asynchronous handshake circuit is arranged to receive the input image from the receiving circuit according to a receiving timing. The super resolution scale-up model is arranged to scale up the input image to generate an output image with a second pixel clock frequency. The second asynchronous handshake circuit is arranged to output the output image to the transmitting circuit according to a transmitting timing to transmit the output image, wherein the first asynchronous handshake circuit, the super resolution scale-up model, and the second asynchronous handshake circuit operate at a clock frequency independent of the first pixel clock frequency and the second pixel clock frequency.

Abstract: The present disclosure discloses an image enlarging apparatus having deep learning mechanism. A deep learning circuit includes an image downsizing circuit, an image characteristic analyzing circuit, a weighting reallocating circuit and an image upsizing circuit. The image downsizing circuit downsizes an input image to generate a downsized image. The image characteristic analyzing circuit analyzes the downsized image according to image characteristics to generate categorized images. The weighting reallocating circuit performs weighting reallocating on the categorized images according to image weighting parameters corresponding to the image characteristics to generate weighting reallocated images. The image upsizing circuit upsizes the weighting reallocated images to generate adjusted images. A concatenating circuit concatenates the input image and the adjusted images to generate concatenated images.

Abstract: The present invention provides a chipset for FRC, wherein the chipset includes a first FRC chip and a second FRC chip. The first FRC chip is configured to receive a first part of input image data, and perform a motion compensation on the first part of the input image data to generate a first part of an output image data, wherein a frame rate of the output image data is greater than or equal to a frame rate of the input image data. The second FRC chip is configured to receive a second part of the input image data, and perform the motion compensation on the second part of the input image data to generate a second part of the output image data; wherein the first part and the second part of the output image data are combined into the complete output image data for displaying on a display panel.

Abstract: A method for training a super-resolution model, a super-resolution method, and a system are provided, and the super-resolution method and the system are implemented through an AI super-resolution model that is trained by the method. In the method, an input image is provided, and a magnification ratio and an image quality threshold are set. Pixel values of the input image are retrieved, and image features of the input image are extracted. Multiple channel images are obtained through a super-resolution model based on the image features and the magnification ratio. Phase information can be obtained according to the magnification ratio and positions of output pixels, and the phase information is used to obtain masks mapping to the channel images. Therefore, an output image can be reshuffled. After a comparison with the image quality threshold, model parameters of the output image can be assessed for training the AI super-resolution model.

Abstract: The embodiments of the disclosure provide a method for determining an ambient light luminance, a host, and a computer readable storage medium. The method includes: obtaining a first frame and a second frame, wherein the first frame comprises a plurality of first regions of interest (ROI), the second frame comprises a plurality of second ROIs, and the first ROIs respectively correspond to the second ROIs; in response to determining that the first ROIs comprise at least one specific ROI satisfying a predetermined condition and at least one first candidate ROI, obtaining at least one second candidate ROI among the second ROIs, wherein the at least one second candidate ROI respectively correspond to the at least one specific ROI; and determining the ambient light luminance based on the at least one first candidate ROI and the at least one second candidate ROI.

Abstract: A method for labeling an image object and a circuit system are provided. In the method, an object classification method is used to segment an image into one or more regions. Each of the regions can be classified into one classification assigned with a classification label. A depth estimation method is used to estimate a depth of each pixel of the image. Whether or not the depth of the pixel matches the classification of the region to which the pixel belongs is determined. When the depth of the pixel matches the classification of the region, a post-processing process is performed on the image based on weights assigned to the regions according to the classification label of the region. Conversely, when the depth of the pixel does not match the classification of the region, the pixel is regarded as noise that does not require the post-processing process.

Abstract: The present invention provides a signal processing device including a receiver, a signal processor and a transmitter. The receiver is configured to receive a first video signal. The signal processor is coupled to the receiver and configured to support a plurality of scene modes, select a current scene mode form the plurality of scene modes according to a user input, and operate in the current scene mode to process the first video signal to generate a second video signal. The transmitter is configured to output the second video signal.

Abstract: An integrated circuit layout and an integrated circuit layout method for a filter are provided. The method includes: determining a structure of a target filter circuit that includes a capacitor and a first optional component; reserving a first circuit region; disposing the first optional component in the first circuit region, and electrically connecting the first optional component, through a plurality of first wires located in a first metal layer, to a plurality of first external nodes that are outside the first circuit region; electrically connecting the plurality of first external nodes to a plurality of second wires located in a second metal layer, respectively, in which the second wires are disposed around the first circuit region; and disposing the capacitor in the first circuit region and above the first optional component.