Abstract: A driving circuit for driving a light source and a projection device are provided. The driving circuit includes a power converter, a detection circuit, and a control circuit. The power converter provides a driving power to the light source. The detection circuit provides a feedback signal according to a current value of the light source. The control circuit receives an operation command and the feedback signal. The control circuit determines whether the driving circuit enters a light-load state according to at least one of the operation command and the feedback signal. When the driving circuit is determined to enter the light-load state, the control circuit controls the power converter to decrease a current value of the driving power and controls the power converter to increase a switching frequency of the driving power. The driving circuit and the projection device may prevent the light source from flickering under the light-load state.

Abstract: An electronic package is provided and includes a substrate structure, an electronic element disposed on the substrate structure and an encapsulation layer encapsulating the electronic element, where at least one functional circuit is formed on a surface of a substrate body of the substrate structure, and a wire having a smaller width is arranged on a boundary line at a junction between an encapsulation area and a peripheral area, so that when a mold for forming the encapsulation layer is formed to cover the substrate structure, the mold will create a gap around the wire to serve as an exhaust passage. Therefore, when the encapsulation layer is formed, the exhaust passage can be used to exhaust air, so as to avoid problems such as the occurrence of voids or overflows of the encapsulation layer.

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes first and second gates, a dielectric hump, a first spacer, a charge storage layer, a gate dielectric layer, a high-k layer and doped regions. The first and the second gates are disposed on a substrate. The dielectric hump is disposed on the substrate between the first gate and the second gate. The first spacer is disposed on a sidewall of the dielectric hump. The charge storage layer is disposed between the first gate and the substrate. The gate dielectric layer is disposed between the second gate and the substrate. The high-k layer is disposed between the first gate and the charge storage layer and between the second gate and the gate dielectric layer. The doped regions are disposed in the substrate at two sides of the first gate and at two sides of the second gate.

Abstract: A biocompatible magnetic material containing an iron oxide nanoparticle and one or more biocompatible polymers, each having formula (I) below, covalently bonded to the iron oxide nanoparticle: in which each of variables R, L, x, and y is defined herein, the biocompatible magnetic material contains 4-15% Fe(II) ions relative to the total iron ions. Also disclosed in a method of preparing the biocompatible magnetic material.

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes a substrate having first and second regions, first and second isolation structures in the substrate, a charge storage layer on the substrate, first and second gates and doped regions. The first isolation structures define first active areas in the first region. A top surface of the first isolation structure is higher than that of the substrate. The second isolation structures define second active areas in the second region. A top surface of the second isolation structure is lower than that of the substrate. The first gate is on the charge storage layer in the first active area. The second gate is on the charge storage layer in the second active area. The doped regions are in the substrate at two sides of the first gate and at two sides of the second gate.

Abstract: A semiconductor device includes a substrate, an isolation structure, a conductive structure, and a first contact structure. The isolation structure is disposed in the substrate. The conductive structure is disposed on the isolation structure. The conductive structure extends upwards from the isolation structure, in which the first contact structure has a top portion on the conductive structure and a bottom portion in contact with the isolation structure.

Abstract: A method for producing carbon nanotubes includes subjecting a plastic material and an acidic zeolite to a pyrolysis reaction so as to form a hydrocarbon compound having 1 to 6 carbon atoms. The acidic zeolite has a molar ratio of SiO2 to Al2O3 ranging from 5.1:1 to 80:1. Another method for producing carbon nanotubes includes subjecting a hydrocarbon compound having 1 to 6 carbon atoms and a catalyst to a catalysis reaction so as to obtain the carbon nanotubes. The catalyst includes a support and a plurality of ferromagnetic nanoparticles supported on the support. The ferromagnetic nanoparticles have an average diameter ranging from 20 nm to 30 nm, and are derived from acetylacetonate of a ferromagnetic transition metal.

Abstract: A pneumatic puller includes a shell unit, a pulling member that has a fixed section and an exposed section, a piston that is fixedly connected to the fixed section, a directional valve assembly that is movably mounted to the piston, and a cylinder that is sleeved on the fixed section. The cylinder and the piston define a first chamber and a second chamber. The cylinder is movable along the fixed section between a first reverse position and a second reverse position relative to the piston when urged by pressure of a gas. The cylinder abuts against one side of the piston and the directional valve assembly releases the gas into the second chamber when the cylinder is in the first reverse position. The cylinder moves along the fixed section away from the exposed section and hits the piston when moving from the first reverse position to the second reverse position.

Abstract: A substrate structure is provided, in which an insulating protection layer is formed on a substrate body having a plurality of electrical contact pads, and the insulating protection layer has a plurality of openings corresponding to the plurality of exposed electrical contact pads, and the insulating protection layer is formed with a hollow portion surrounding a partial edge of at least one of the electrical contact pads at at least one of the openings, so as to reduce the barrier of the insulating protection layer.

Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

Abstract: In some embodiments, the present disclosure relates to a method that includes forming a dielectric layer over a conductive structure on a substrate. A removal process is performed to remove a portion of the dielectric layer to expose a portion of the conductive structure. The substrate is transported into a cleaning chamber having a wafer chuck below a bell jar structure. A cleaning process is performed to clean the exposed portion of the conductive structure by turning on a noble gas source to introduce a noble gas within the cleaning chamber, turning on an oxygen gas source to introduce oxygen within the cleaning chamber, applying a first bias to a plasma coil to form a plasma gas, and applying a second bias to the wafer chuck. The substrate is removed from the cleaning chamber. A conductive layer is formed over the dielectric layer and coupled to the conductive structure.

Abstract: Systems and methods of inspecting a sample using a charged-particle beam apparatus with enhanced probe current and high current density of the primary charged-particle beam are disclosed. The apparatus includes a charged-particle source, a first condenser lens configured to condense the primary charged-particle beam and operable in a first mode and a second mode, wherein: in the first mode, the first condenser lens is configured to condense the primary charged-particle beam, and in the second mode, the first condenser lens is configured to condense the primary charged-particle beam sufficiently to form a crossover along the primary optical axis. The apparatus further includes a second condenser lens configured to adjust a first beam current of the primary charged-particle beam in the first mode and adjust a second beam current of the primary charged-particle beam in the second mode, the second beam current being larger than the first beam current.

Abstract: The present disclosure is related to an intelligent charging management system, a charging management device, and a charging management method. The charging management device is used to execute the charging management method for determining a chargeable power value of the electric vehicle according to an operation mode of the electric vehicle and an available capacity of a charging point, and determining a charging parking lot for providing to the electric vehicle according to the chargeable power value of the electric vehicle and available charging parking lots of the charging point. In the way, the charging power and charging parking lots of the charging point can be allocated according to the charging requirements of electric vehicles, electric vehicles can be accurately and efficiently charged and the damage caused by charging current to the battery is reduced, so as the purpose for improving charging efficiency of the charging point is determined.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.

Abstract: A method of manufacturing a semiconductor structure with flush shallow trench isolation and gate oxide, including performing a first etching process to remove a pad oxide layer at one side of a STI and recess the substrate, the first etching process also forms a recess portion not covered by the first etching process and a protruding portion covered by the first etching process on the STI, forming a gate oxide layer on the recessed substrate, performing a second etching process to remove the protruding portion and the pad oxide layer and a first oxide layer on a drain region, performing a third etching process to remove a part of the STI and a second oxide layer, so that a top plane of the STI is flush with the gate oxide layer.

Abstract: A substrate structure is provided, in which an insulating protection layer is formed on a substrate body having a plurality of electrical contact pads, and the insulating protection layer has a plurality of openings corresponding to the plurality of exposed electrical contact pads, and the insulating protection layer is formed with a hollow portion surrounding a partial edge of at least one of the electrical contact pads at at least one of the openings, so as to reduce the barrier of the insulating protection layer.

Abstract: A light emitting diode includes a substrate and a semiconductor light emitting stack layer. The semiconductor light emitting stack layer is disposed on the substrate, and the substrate has four sidewalls, an upper surface, and a lower surface. At least one sidewall is provided with a first laser dotting region and a second laser dotting region. The first laser dotting region includes first laser dots, and the second laser dotting region includes second laser dots. A stress crack is present between the first laser dotting region and the second laser dotting region. A first distance D1 is present between the first laser dotting region and the stress crack, a second distance D2 is present between the second laser dotting region and the stress crack, and 0.7D2<D1<1.3D2.

Abstract: In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defining a processing chamber. Within the processing chamber is a wafer chuck configured to hold a substrate. Further, a bell jar structure is arranged over the wafer chuck such that an opening of the bell jar structure faces the wafer chuck. A plasma coil is arranged over the bell jar structure. An oxygen source coupled to the processing chamber and configured to input oxygen gas into the processing chamber.

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.