Patents by Inventor Chia-Wen Chang

Chia-Wen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250190162
    Abstract: A display system and a display method are provided. The display system includes a first display device, a first transmission cable and a second display device. The first transmission cable connects between the first display device and the second display device. The first display device receives a first command and an image signal. The first display device generates a first control signal according to the first command. A splicing mode of the first display device is turned on, the first display device provides the first control signal and the image signal to the second display device. The first display device displays a first image. The second display device displays a second image. A predetermined displaying image corresponding to the image signal comprises the first image and the second image.
    Type: Application
    Filed: November 13, 2024
    Publication date: June 12, 2025
    Applicant: Optoma Corporation
    Inventors: Chia-Wen Chang, Yen-Hsiang Hung
  • Patent number: 12211836
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wen Chang, Hong-Nien Lin, Chien-Hsing Lee, Chih-Sheng Chang, Ling-Yen Yeh, Wilman Tsai, Yee-Chia Yeo
  • Publication number: 20240190147
    Abstract: An example printer including: a platen roller; a bushing connected to the platen roller, the bushing having a wing extending radially from the bushing; and a lower frame including: a channel to receive the platen roller in an operational position in which the platen roller is configured to feed media for a print head of the printer; an end piece defining an end of the channel, the end piece having an opening to receive the bushing when the platen roller is in the operational position; and a tab on the end piece, the tab positioned to interface with the wing of the bushing to secure the bushing in the opening such that the platen roller is maintained in the operational position within the channel.
    Type: Application
    Filed: February 16, 2024
    Publication date: June 13, 2024
    Inventors: Randal Wong Mun Hon, Shu-Hsun Jason Chiang, Kuan-Ying Lu, Chia-Wen Chang, Hsinghan Tsai
  • Patent number: 11904603
    Abstract: An example printer including: a platen roller; a bushing connected to the platen roller, the bushing having a wing extending radially from the bushing; and a lower frame including: a channel to receive the platen roller in an operational position in which the platen roller is configured to feed media for a print head of the printer; an end piece defining an end of the channel, the end piece having an opening to receive the bushing when the platen roller is in the operational position; and a tab on the end piece, the tab positioned to interface with the wing of the bushing to secure the bushing in the opening such that the platen roller is maintained in the operational position within the channel.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: February 20, 2024
    Assignee: Zebra Technologies Corporation
    Inventors: Randal Mun Hon Wong, Shu-Hsun Chiang, Kuan-Ying Lu, Chia-Wen Chang, Hsinghan Tsai
  • Publication number: 20230343781
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 26, 2023
    Inventors: Chia-Wen CHANG, Hong-Nien LIN, Chien-Hsing LEE, Chih-Sheng CHANG, Ling_Yen YEH, Wilman TSAI, Yee-Chia YEO
  • Patent number: 11728332
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wen Chang, Hong-Nien Lin, Chien-Hsing Lee, Chih-Sheng Chang, Ling-Yen Yeh, Wilman Tsai, Yee-Chia Yeo
  • Publication number: 20230234378
    Abstract: An example printer including: a platen roller; a bushing connected to the platen roller, the bushing having a wing extending radially from the bushing; and a lower frame including: a channel to receive the platen roller in an operational position in which the platen roller is configured to feed media for a print head of the printer; an end piece defining an end of the channel, the end piece having an opening to receive the bushing when the platen roller is in the operational position; and a tab on the end piece, the tab positioned to interface with the wing of the bushing to secure the bushing in the opening such that the platen roller is maintained in the operational position within the channel.
    Type: Application
    Filed: January 27, 2022
    Publication date: July 27, 2023
    Inventors: Randal Mun Hon Wong, Shu-Husn Chiang, Kuan-Ying Lu, Chia-Wen Chang, Hsinghan Tsai
  • Patent number: 11217304
    Abstract: A method of operating a synapse array includes applying a pulse sequence to a resistor coupled between a row and a column of the synapse array, and in response to the applying the pulse sequence, lowering a conductance level of the resistor. Each pulse of the pulse sequence includes a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge, and applying the pulse sequence includes increasing the pulse number while increasing one of the amplitude, the pulse width, or the trailing edge duration.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Sheng Chen, Jau-Yi Wu, Chia-Wen Chang
  • Publication number: 20210343705
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
    Type: Application
    Filed: June 21, 2021
    Publication date: November 4, 2021
    Inventors: Chia-Wen CHANG, Hong-Nien LIN, Chien-Hsing LEE, Chih-Sheng CHANG, Ling-Yen YEH, Wilman TSAI, Yee-Chia YEO
  • Patent number: 11114540
    Abstract: A semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch and the second switch are negative capacitance FET.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: September 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Hsing Lee, Chih-Sheng Chang, Wilman Tsai, Chia-Wen Chang, Ling-Yen Yeh, Carlos H. Diaz
  • Publication number: 20210210137
    Abstract: A method of operating a synapse array includes applying a pulse sequence to a resistor coupled between a row and a column of the synapse array, and in response to the applying the pulse sequence, lowering a conductance level of the resistor. Each pulse of the pulse sequence includes a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge, and applying the pulse sequence includes increasing the pulse number while increasing one of the amplitude, the pulse width, or the trailing edge duration.
    Type: Application
    Filed: March 19, 2021
    Publication date: July 8, 2021
    Inventors: Yu-Sheng CHEN, Jau-Yi WU, Chia-Wen CHANG
  • Patent number: 11043489
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wen Chang, Hong-Nien Lin, Chien-Hsing Lee, Chih-Sheng Chang, Ling-Yen Yeh, Wilman Tsai, Yee-Chia Yeo
  • Patent number: 10971223
    Abstract: A method includes applying a pulse sequence to a PCM device, each pulse of the pulse sequence including a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge. Applying the pulse sequence includes increasing the pulse number while increasing at least one of the amplitude, the pulse width, or the trailing edge duration. A conductance level of the PCM device is altered in response to applying the pulse sequence.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Sheng Chen, Jau-Yi Wu, Chia-Wen Chang
  • Patent number: 10937783
    Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wen Chang, Hong-Nien Lin, Chien-Hsing Lee, Chih-Sheng Chang, Ling-Yen Yeh, Wilman Tsai, Yee-Chia Yeo
  • Patent number: 10868132
    Abstract: A semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch and the second switch are negative capacitance FET.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Hsing Lee, Chih-Sheng Chang, Wilman Tsai, Chia-Wen Chang, Ling-Yen Yeh, Carlos H. Diaz
  • Publication number: 20200105342
    Abstract: A method includes applying a pulse sequence to a PCM device, each pulse of the pulse sequence including a pulse number, an amplitude, a leading edge, a pulse width, and a trailing edge, the trailing edge having a duration longer than a duration of the leading edge. Applying the pulse sequence includes increasing the pulse number while increasing at least one of the amplitude, the pulse width, or the trailing edge duration. A conductance level of the PCM device is altered in response to applying the pulse sequence.
    Type: Application
    Filed: August 21, 2019
    Publication date: April 2, 2020
    Inventors: Yu-Sheng CHEN, Jau-Yi WU, Chia-Wen CHANG
  • Publication number: 20200052087
    Abstract: A semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch and the second switch are negative capacitance FET.
    Type: Application
    Filed: November 4, 2019
    Publication date: February 13, 2020
    Inventors: Chien-Hsing LEE, Chih-Sheng CHANG, Wilman TSAI, Chia-Wen CHANG, Ling-Yen YEH, Carlos H. DIAZ
  • Patent number: 10355149
    Abstract: A tandem solar cell module includes a transparent substrate, a first solar cell unit, and a second solar cell unit disposed between the transparent substrate and the first solar cell unit. The first solar cell unit includes a first electrode, a second electrode, and a first absorption layer disposed between the first electrode and the second electrode, and the second solar cell unit includes a third electrode, a fourth electrode, and a second absorption layer disposed between the third electrode and the fourth electrode, wherein the second electrode is located adjacent to the third electrode, and the positions of the second electrode, the third electrode, and the fourth electrode are corresponding to each other.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: July 16, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Wen Chang, Yung-Tsung Liu, Wei-Sheng Lin
  • Publication number: 20190088760
    Abstract: A semiconductor device includes a first potential supply line for supplying a first potential, a second potential supply line for supplying a second potential lower than the first potential, a functional circuit, and at least one of a first switch disposed between the first potential supply line and the functional circuit and a second switch disposed between the second potential supply line and the functional circuit. The first switch and the second switch are negative capacitance FET.
    Type: Application
    Filed: September 18, 2017
    Publication date: March 21, 2019
    Inventors: Chien-Hsing LEE, Chih-Sheng CHANG, Wilman TSAI, Chia-Wen CHANG, Ling-Yen YEH, Carlos H. DIAZ
  • Patent number: 10201982
    Abstract: An example disclosed printer includes a base; a lid hingedly attached to the base movable between a closed position in which the lid is secured to the base, and an open position in which the lid is at least partially separated from the base; a cavity defined between the lid and the base, wherein the cavity is inaccessible when the lid is in the closed position and the cavity is accessible when the lid is in the open position; a ribbon positioning assembly disposed within the cavity that is pivotably attached to at least one of the lid or the base wherein the ribbon positioning assembly is configured to move between a printing position when the lid is in the closed position, and an accessible position when the lid is in the open position, wherein the ribbon positioning assembly comprises a ribbon tensioning mechanism.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: February 12, 2019
    Assignee: ZIH Corp.
    Inventors: Randal Wong, Petrica D. Balcan, Shu-Hsun Chiang, Kuan-Ying Lu, Chia-Wen Chang