Patents by Inventor Chia Wen Chen

Chia Wen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240395605
    Abstract: A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
  • Patent number: 12153350
    Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Gun Liu, Huicheng Chang, Chia-Cheng Chen, Jyu-Horng Shieh, Liang-Yin Chen, Shu-Huei Suen, Wei-Liang Lin, Ya Hui Chang, Yi-Nien Su, Yung-Sung Yen, Chia-Fong Chang, Ya-Wen Yeh, Yu-Tien Shen
  • Publication number: 20240383268
    Abstract: A laser colored product, a laser coloring method therefor, and a laser coloring system using the same are provided. The laser coloring method comprises the following steps. First, provide a processing workpiece which includes a processing part, and the processing part includes a pattern region. The processing part within the pattern region includes an inner portion and an outer layer, and the outer layer includes metal materials. Use the laser coloring system to irradiate the outer layer of the pattern region in stages to convert the outer layer of the pattern region into a metal color pattern layer. The metal color pattern layer includes metal materials or metal compounds of metal materials, and the metal color pattern layer includes a plurality of pixel units arranged in arrays, wherein each of the pixel units includes a pixel color, and each of the pixel units has a pixel width or a pixel length between 1 ?m to 500 ?m.
    Type: Application
    Filed: December 27, 2023
    Publication date: November 21, 2024
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Hung-Wen Chen, Chia-Hung Chou, Yi-Jiun Shen, Chien-Hung Chen
  • Publication number: 20240387275
    Abstract: A method of fabricating a semiconductor device is described. The method includes forming a plurality of fins over a substrate, and forming dummy gates patterned over the fins. Each dummy gate has a spacer on sidewalls of the patterned dummy gates. The method also includes forming recesses in the fins by using the patterned dummy gates as a mask, forming a passivation layer over the fins and in the recesses in the fins, and patterning the passivation layer to leave a remaining passivation layer in some of the recesses in the fins.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Chia-Hao Yu, Hsiao Wen Lee
  • Patent number: 12148671
    Abstract: A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: November 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Chia-Hao Yu, Hsiao Wen Lee
  • Publication number: 20240379433
    Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu-Shih Wang, Ya-Yi Cheng, I-Li Chen
  • Patent number: 12143580
    Abstract: Video processing methods and apparatuses in a video encoding or decoding system for processing a video picture partitioned into blocks with one or more partition constraints. The video encoding or decoding system receives input data of a current block and checks whether a predefined splitting type is allowed to partition the current block according to first and second constraints. The first constraint restricts each sub-block partitioned from the current block to be completely contained in one pipeline unit, and the second constraint restricts each sub-block partitioned from the current block to contain one or more complete pipeline units. The pipeline units are non-overlapping units in the video picture designed for pipeline processing. The current block is not partitioned by the predefined splitting type if any sub-block partitioned by the predefined splitting type violates both the first and second constraints. The system encodes or decodes the current block.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: November 12, 2024
    Assignee: HFI INNOVATION INC.
    Inventors: Chia-Ming Tsai, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
  • Patent number: 12130462
    Abstract: A light guide plate, a backlight module and a display device are provided. The light guide plate includes a main body and an optical layer. The main body has a light-incident surface, a side surface and an optical surface. The light-incident surface and the side surface are respectively connected to the optical surface. The optical layer is correspondingly disposed on the side surface of the main body. In a reflectance characteristic of the optical layer, a total reflectance of the reflectance characteristic is composed of the diffuse reflectance and the parallel reflectance. The percentage value of the parallel reflectance to the total reflectance is less than 45 and larger than 25, including the end point.
    Type: Grant
    Filed: June 26, 2023
    Date of Patent: October 29, 2024
    Assignee: Radiant Opto-Electronics Corporation
    Inventors: I-Wen Fang, Chia-Ying Chen, Yen-Chang Lee, Chun-Hsien Li
  • Patent number: 12125889
    Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Yeh Chen, Wei-Yang Lee, Chia-Pin Lin, Da-Wen Lin
  • Patent number: 12119053
    Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: October 15, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Jen-Yang Hsueh, Ling-Hsiu Chou, Chih-Yang Hsu
  • Publication number: 20240335493
    Abstract: The present invention is a mung bean hull extract with antiviral effect, and the mung bean hull extract achieves antiviral effect by inhibiting ?-glucosidase and neuraminidase. The present invention also relates to a method for extracting the mung bean hull extract with antiviral effect and applications of the extract obtained by the method.
    Type: Application
    Filed: June 18, 2024
    Publication date: October 10, 2024
    Inventors: Hui-Wen CHEN, Feng-Ling YU, Ying-Nien HUNG, Chia-Chen PI
  • Publication number: 20240330091
    Abstract: An information handling system may include a processor, one or more audio speakers configured to play back audible audio signals, and a basic input/output system (BIOS) comprising a program of instructions comprising boot firmware configured to be the first code executed by the processor when the information handling system is booted or powered on in order to initialize the information handling system for operation. The BIOS may be further configured to monitor for an error occurring during execution of the BIOS and responsive to an error occurring during execution of the BIOS, cause the one or more audio speakers to play back a sequence of one or more multi-frequency audio signals encoding an identity of the error.
    Type: Application
    Filed: March 27, 2023
    Publication date: October 3, 2024
    Applicant: Dell Products L.P.
    Inventors: Huang-Lung CHEN, Daniel L. SMYTHIA, Chia-Wen MA, Chia-Hao CHANG, Chi-Hsiu KAO, Chung-Jung WU
  • Patent number: 12100617
    Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: September 24, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Janbo Zhang, Chao-Wei Lin, Chia-Yi Chu, Yu-Cheng Tung, Ken-Li Chen, Tsung-Wen Chen
  • Publication number: 20240313119
    Abstract: A semiconductor structure includes a first pair of source/drain features (S/D), a first stack of channel layers connected to the first pair of S/D, a second pair of S/D, and a second stack of channel layers connected to the second pair of S/D. The first pair of S/D each include a first epitaxial layer having a first dopant, a second epitaxial layer having a second dopant and disposed over the first epitaxial layer and connected to the first stack of channel layers, and a third epitaxial layer having a third dopant and disposed over the second epitaxial layer. The second pair of S/D each include a fourth epitaxial layer having a fourth dopant and connected to the second stack of channel layers, and a fifth epitaxial layer having a fifth dopant and disposed over the fourth epitaxial layer. The first dopant through the fourth dopant are of different species.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
  • Publication number: 20240304531
    Abstract: A semiconductor device includes a die, a redistribution layer (RDL) structure including a first polymer layer, a second polymer layer and a UBM layer. The die is encapsulated by an encapsulant. The RDL structure is disposed over the encapsulant. The second polymer layer is disposed on the first polymer layer, wherein a transmittance of the second polymer layer is smaller than a transmittance of the first polymer layer. The UBM layer is disposed over and electrically connected to the RDL structure, wherein the UBM layer is disposed in the first polymer layer and the second polymer layer.
    Type: Application
    Filed: March 9, 2023
    Publication date: September 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: RUI-WEN SONG, Po-Yuan Teng, Hao-Yi Tsai, Chia-Hung Liu, Shih-Wei Chen
  • Publication number: 20240304551
    Abstract: Devices with aluminum structures and methods of fabrication are provided. An exemplary device includes an interconnect structure and an aluminum structure electrically connected to the interconnect structure. The aluminum structure includes a first aluminum layer, a migration barrier layer over the first aluminum layer, and a second aluminum layer over the migration barrier layer.
    Type: Application
    Filed: March 7, 2023
    Publication date: September 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pang Kuo, Sean Yang, Yue-Guo Lin, Tsai Hsi-Chen, Chi-Feng Lin, Hung-Wen Su
  • Publication number: 20240291985
    Abstract: Video processing methods and apparatuses in a video encoding or decoding system. A method receives input data associated with a current block in a current picture, determines if the current block is an out-of-bounds node, wherein the out-of-bounds node is a coding tree node of the current picture with a block region across a current picture boundary, and determines whether the current block is larger than a predefined size. The method further determines an inferred splitting type if the current block is an out-of-bounds node and the current block is larger than the predefined size and applies the inferred splitting type to split the current block into child blocks if the current block is an out-of-bounds node and the current block is larger than the predefined size, and then adaptively splitting each child block into one or more leaf blocks.
    Type: Application
    Filed: May 9, 2024
    Publication date: August 29, 2024
    Inventors: Chia-Ming TSAI, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG, Shih-Ta HSIANG
  • Publication number: 20240287589
    Abstract: Compositions including photoreactive and cleavable probes and methods of using the probes. The probes may include a tag conjugatable to a label, a cleavable linker linkable to a bait molecule, and a light activated warhead, which may be configured to covalently bond an anchoring strand to a probing strand upon application of light energy. The compositions and methods may be useful for analyzing biomolecules, such as identifying proximal molecules in cell or tissue samples.
    Type: Application
    Filed: March 20, 2024
    Publication date: August 29, 2024
    Inventors: Chih-Wei CHANG, Hsiang-Ju KAI, Chia-Wen CHUNG, Yi-De CHEN, Jung-Chi LIAO
  • Publication number: 20240282575
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 22, 2024
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo-Bin Huang
  • Publication number: 20240282272
    Abstract: A display device and control method thereof. The display device includes a housing, a display assembly, and a plurality of light-emitting components. The housing has a front surface, an outer peripheral surface and a mounting opening. The outer peripheral surface is connected to the front surface. The mounting opening is located on the front surface and surrounded by the outer peripheral surface. The display assembly is disposed in the mounting opening and exposed to outside. The plurality of light-emitting components are fixed to the housing. A light emitted from the plurality of light-emitting components is partially emitted along a normal direction of the outer peripheral surface, and is partially emitted along a normal direction of the front surface.
    Type: Application
    Filed: March 30, 2023
    Publication date: August 22, 2024
    Applicants: MICRO-STAR INT’L CO.,LTD., MSI COMPUTER (SHENZHEN) CO.,LTD.
    Inventors: Chun-Te YEH, Chung-Wen CHEN, Chia-Liang HOU