Patents by Inventor Chia Wen Chen

Chia Wen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12294030
    Abstract: A semiconductor structure includes a first pair of source/drain features (S/D), a first stack of channel layers connected to the first pair of S/D, a second pair of S/D, and a second stack of channel layers connected to the second pair of S/D. The first pair of S/D each include a first epitaxial layer having a first dopant, a second epitaxial layer having a second dopant and disposed over the first epitaxial layer and connected to the first stack of channel layers, and a third epitaxial layer having a third dopant and disposed over the second epitaxial layer. The second pair of S/D each include a fourth epitaxial layer having a fourth dopant and connected to the second stack of channel layers, and a fifth epitaxial layer having a fifth dopant and disposed over the fourth epitaxial layer. The first dopant through the fourth dopant are of different species.
    Type: Grant
    Filed: May 24, 2024
    Date of Patent: May 6, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
  • Publication number: 20250134621
    Abstract: A tooth surface laser processing method and a laser processing system for the same are provided. The laser processing method adapted for a tooth comprises the following steps. The tooth is first checked up to obtain tooth information so that one may determine whether the tooth is suitable for laser processing steps. A laser processing system is chosen according to the tooth information, and laser parameters are selected and loaded according to the part on the surface of the tooth and the degree required to be processed. The laser processing steps are performed on the surface of the tooth by the laser processing system to form a laser processed structure on the surface of the tooth. The laser processed structure comprises a plurality of micro-grooves and a plurality of micro-bumps therebetween.
    Type: Application
    Filed: March 26, 2024
    Publication date: May 1, 2025
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: HUNG-WEN CHEN, YI-JIUN SHEN, CHIA-HUNG CHOU, CHIEN-HUNG CHEN
  • Patent number: 12289525
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion, a fixed portion, and a driving assembly. The movable portion is used to connect the optical element. The movable portion may move relative to the fixed portion. The driving assembly is used to drive the movable portion to move relative to the fixed portion.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: April 29, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Hsiao-Hsin Hu, Chih-Wen Chiang, Chia-Che Wu, Yu-Chiao Lo, Yi-Ho Chen, Chao-Chang Hu, Sin-Jhong Song
  • Patent number: 12289040
    Abstract: A driving circuit for driving a light source and a projection device are provided. The driving circuit includes a power converter, a detection circuit, and a control circuit. The power converter provides a driving power to the light source. The detection circuit provides a feedback signal according to a current value of the light source. The control circuit receives an operation command and the feedback signal. The control circuit determines whether the driving circuit enters a light-load state according to at least one of the operation command and the feedback signal. When the driving circuit is determined to enter the light-load state, the control circuit controls the power converter to decrease a current value of the driving power and controls the power converter to increase a switching frequency of the driving power. The driving circuit and the projection device may prevent the light source from flickering under the light-load state.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: April 29, 2025
    Assignee: Coretronic Corporation
    Inventors: Chia-Wen Hsu, Chen-Wang Chen, Tung-Min Lee
  • Publication number: 20250133761
    Abstract: A semiconductor structure includes a substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers are over the substrate and spaced apart from each other in a Z-direction. The source/drain features are over the substrate. The semiconductor layers are between the source/drain features. The metal oxide layers are on top surfaces and bottom surfaces of the semiconductor layers. The gate structure covers and is in contact with center portions of the metal oxide layers on top surfaces and bottom surfaces of the semiconductor layers.
    Type: Application
    Filed: December 30, 2024
    Publication date: April 24, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hao LIN, Chia-Hung CHOU, Chih-Hsuan CHEN, Ping-En CHENG, Hsin-Wen SU, Chien-Chih LIN, Szu-Chi YANG
  • Publication number: 20250125189
    Abstract: A method for manufacturing an interconnect structure includes: forming a first dielectric layer; forming a mask; patterning the first dielectric layer through the mask to form a trench, an inner surface of the trench having two first portions opposite to each other along an X direction, two second portions opposite to each other along a Y direction, and a bottom portion; forming a second dielectric layer over the mask and the patterned first dielectric layer, and along an inner surface of the trench; etching the second dielectric layer by directing an etchant in a predetermined direction such that a first part of the second dielectric layer on the two first portions and the bottom portion is removed, and a second part of the second dielectric layer on the second portions of the trench remains and is formed into two reinforcing spacers; and forming a trench-filling element.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 17, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Chih-Wei LU, Hwei-Jay CHU, Yu-Teng DAI, Hsin-Chieh YAO, Yung-Hsu WU, Li-Ling SU, Chia-Wei SU, Hsin-Ping CHEN
  • Publication number: 20250125251
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, strained layers, source/drain contact patterns, a gate contact via, and source/drain contact vias. The gate structure is disposed over the semiconductor substrate. The strained layers are disposed aside the gate structure. The source/drain contact patterns are disposed on and electrically connected to the strained layers. Top surfaces of the source/drain contact patterns are coplanar with a top surface of the gate structure. The gate contact via is disposed on and electrically connected to the gate structure. The source/drain contact vias are disposed on and electrically connected to the source/drain contact patterns.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Ling Su, Chia-Wei Su, Tsu-Chun Kuo, Wei-Hao Liao, Hsin-Ping Chen, Yung-Hsu Wu, Ming-Han Lee, Shin-Yi Yang, Chih Wei LU, Hsi-Wen Tien, Meng-Pei Lu
  • Publication number: 20250120087
    Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes first and second gates, a dielectric hump, a first spacer, a charge storage layer, a gate dielectric layer, a high-k layer and doped regions. The first and the second gates are disposed on a substrate. The dielectric hump is disposed on the substrate between the first gate and the second gate. The first spacer is disposed on a sidewall of the dielectric hump. The charge storage layer is disposed between the first gate and the substrate. The gate dielectric layer is disposed between the second gate and the substrate. The high-k layer is disposed between the first gate and the charge storage layer and between the second gate and the gate dielectric layer. The doped regions are disposed in the substrate at two sides of the first gate and at two sides of the second gate.
    Type: Application
    Filed: November 6, 2023
    Publication date: April 10, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Jen Yang Hsueh, Chien-Hung Chen, Tzu-Ping Chen, Chia-Hui Huang, Chia-Wen Wang, Chih-Yang Hsu, Ling Hsiu Chou
  • Publication number: 20250112087
    Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 3, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hwei-Jay CHU, Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Tzu-Hui WEI, Chih Wei LU, Chan-Yu LIAO, Li-Ling SU, Chia-Wei SU, Yung-Hsu WU, Hsin-Ping CHEN
  • Publication number: 20250113488
    Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes a substrate having first and second regions, first and second isolation structures in the substrate, a charge storage layer on the substrate, first and second gates and doped regions. The first isolation structures define first active areas in the first region. A top surface of the first isolation structure is higher than that of the substrate. The second isolation structures define second active areas in the second region. A top surface of the second isolation structure is lower than that of the substrate. The first gate is on the charge storage layer in the first active area. The second gate is on the charge storage layer in the second active area. The doped regions are in the substrate at two sides of the first gate and at two sides of the second gate.
    Type: Application
    Filed: October 25, 2023
    Publication date: April 3, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Chien-Hung Chen, Chia-Hui Huang, Ling Hsiu Chou, Jen Yang Hsueh, Chih-Yang Hsu
  • Publication number: 20250098226
    Abstract: Present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor fin and a metal gate. The semiconductor fin has a first portion and a second portion over the first portion. A height of the second portion is greater than a width of the second portion. The metal gate has a bottom portion, an upper portion, and a lateral portion connecting the bottom portion and the upper portion. The bottom portion is between the first portion and the second portion of the semiconductor fin, and the upper portion is over the second portion of the semiconductor fin.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: CHIA-MING HSU, YI-JING LI, CHIH-HSIN KO, KUANG-HSIN CHEN, DA-WEN LIN, CLEMENT HSINGJEN WANN
  • Publication number: 20250075918
    Abstract: A recessed induction cooker with a heat insulation protection pad structure and a temperature detection device includes: a heat insulation protection pad, having at least one through hole; a recessed induction cooker, having a housing, a support, a coil and an arched panel; and a temperature detection module, having a temperature detector, a central processing unit and a circuit controller, wherein the temperature detector is for detecting a temperature of the arched panel to generate a temperature value, the central processing unit has a threshold unit and a comparison unit, the threshold unit pre-stores a temperature threshold, the comparison unit compares the temperature threshold with the temperature value, and the central processing unit drives the circuit controller to control the coil to stop heating when the temperature value is greater than or equal to the temperature threshold.
    Type: Application
    Filed: September 4, 2023
    Publication date: March 6, 2025
    Inventors: Chia-Pin CHEN, Wei-Wen HUANG
  • Publication number: 20250080756
    Abstract: A method and apparatus for inter prediction in video coding system are disclosed. According to the method, one or more model parameters of one or more cross-color models for the second-color block are determined. Then, cross-color predictors for the second-color block are determined, wherein one cross-color predictor value for the second-color block is generated for each second-color pixel of the second-color block by applying said one or more cross-color models to corresponding reconstructed or predicted first-color pixels. The input data associated with the second-color block is encoded using prediction data comprising the cross-color predictors for the second-color block at the encoder side, or the input data associated with the second-color block is decoded using the prediction data comprising the cross-color predictors for the second-color block at the decoder side.
    Type: Application
    Filed: December 20, 2022
    Publication date: March 6, 2025
    Inventors: Man-Shu CHIANG, Olena CHUBACH, Yu-Ling HSIAO, Chia-Ming TSAI, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20250072080
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer on the gate structure, forming a patterned mask on the gate structure and one side of the gate structure, removing the first spacer on another side of the gate structure, and then forming a source/drain region adjacent to two sides of the gate structure.
    Type: Application
    Filed: September 25, 2023
    Publication date: February 27, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Yih Chen, Yi-Wen Chen, Chia-Chen Sun, Wei-Chung Sun, Wan-Ching Lee
  • Patent number: 12235614
    Abstract: The present disclosure provides a molding system for fabricating a FRP composite article. The molding system includes a detector, a resin dispenser, a processing module, and a molding machine. The detector is configured to capture a graph of a woven fiber from a top view. The resin dispenser is configured to provide a resin to the woven fiber to form a FRP. The processing module is configured to receive the graph and a plurality of parameters of the FRP. The processing module includes a CNN model, and is configured to use the CNN model to obtain a plurality of predicted mechanical properties of the FRP according to the graph and the plurality of parameters of the FRP. The molding machine is configured to mold the FRP to fabricate the FRP composite article according to the plurality of predicted mechanical properties.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: February 25, 2025
    Assignee: CORETECH SYSTEM CO., LTD.
    Inventors: Chi-Hua Yu, Mao-Ken Hsu, Yi-Wen Chen, Li-Hsuan Shen, Chih-Chung Hsu, Chia-Hsiang Hsu, Rong-Yeu Chang
  • Publication number: 20250063155
    Abstract: A method and apparatus for inter prediction in video coding system are disclosed. According to the method, input data associated with a current block comprising at least one colour block are received. A blending predictor is determined according to a weighted sum of at least two candidate predictions generated based on one or more first hypotheses of prediction, one or more second hypotheses of prediction, or both. The first hypotheses of prediction are generated based on one or more intra prediction modes comprising a DC mode, a planar mode or at least one angular modes. The second hypotheses of prediction are generated based on one or more cross-component modes and a collocated block of said at least one colour block. The input data associated with the colour block is encoded or decoded using the blending predictor.
    Type: Application
    Filed: December 20, 2022
    Publication date: February 20, 2025
    Inventors: Man-Shu CHIANG, Olena CHUBACH, Chia-Ming TSAI, Yu-Ling HSIAO, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Patent number: 12220550
    Abstract: Provided is a device for transdermal delivery of drugs. The device includes a separable substrate and is loaded with dual drugs based on an interpenetrating polymer network hydrogel. Also provided are methods of making and using the transdermal delivery device.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: February 11, 2025
    Assignee: BUDDHIST TZU CHI MEDICAL FOUNDATION
    Inventors: Yu-Shuan Chen, Hsieh-Chih Tsai, Chang-Yi Lee, Haile Fentahun Darge, Shinn-Zong Lin, Tzyy-Wen Chiou, Chia-Yu Chang
  • Publication number: 20250044708
    Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
    Type: Application
    Filed: October 18, 2024
    Publication date: February 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun LIU, Huicheng CHANG, Chia-Cheng CHEN, Jyu-Horng SHIEH, Liang-Yin CHEN, Shu-Huei SUEN, Wei-Liang LIN, Ya Hui CHANG, Yi-Nien SU, Yung-Sung YEN, Chia-Fong CHANG, Ya-Wen YEH, Yu-Tien SHEN
  • Publication number: 20250048555
    Abstract: A circuit board module includes a circuit board and a plurality of capacitors. The circuit board has a plurality of standing feet for erecting on a main board, and the capacitors are symmetrically fixed on a first surface and a second surface opposite to the first surface of the circuit board. An opening is formed on the circuit board of the circuit board module and the opening is located between the capacitors. In addition, an electronic device adopting the circuit board module design is also disclosed herein.
    Type: Application
    Filed: December 7, 2023
    Publication date: February 6, 2025
    Inventors: Hung-Wen CHUEH, Chia-Yu CHEN, Yan-Ru CHEN
  • Publication number: 20250043176
    Abstract: An organic electroluminescent material is used for a sensitizer layer of an organic light-emitting diode. The organic electroluminescent material includes a structure of the following General Formula (1): A is selected from the group consisting of General Formula (2), a carbazole group, and a substituted benzimidazole group. The present invention also discloses an organic light-emitting diode which has a sensitizer layer. The sensitizer layer includes a structure of General Formula (1).
    Type: Application
    Filed: August 2, 2024
    Publication date: February 6, 2025
    Inventors: Tien-Lung CHIU, Man-Kit LEUNG, Chia-Hsun CHEN, Chen-Jun CHU, Chi-Chi CHANG, Yi-Ru HAUNG, Jiun-Haw LEE, Lian-Chun HUANG, Zi-Wen SU, Yuan-Zhen ZUANG, Jing-Xiang HUANG