Abstract: An image sensor including a substrate and an image sensing element is provided. The substrate has an arc surface. The image sensing element is disposed on the arc surface and curved to fit a contour of the arc surface. The image sensing element has a front surface and a rear surface opposite to the front surface and has at least one bonding wire, the bonding wire is connected between the front surface and the substrate, and the rear surface of the image sensing element directly contacts the arc surface. In addition, a manufacturing method of the image sensor is also provided.

Abstract: An image sensor including a substrate and an image sensing element is provided. The substrate has an arc surface. The image sensing element is disposed on the arc surface and curved to fit a contour of the arc surface. The image sensing element has a front surface and a rear surface opposite to the front surface and has at least one bonding wire, the bonding wire is connected between the front surface and the substrate, and the rear surface of the image sensing element directly contacts the arc surface. In addition, a manufacturing method of the image sensor is also provided.

Abstract: An image sensor including a substrate and an image sensing element is provided. The substrate has an arc surface. The image sensing element is disposed on the arc surface and curved to fit a contour of the arc surface. The image sensing element has a front surface and a rear surface opposite to each other and has at least one first conductive via. The rear surface of the image sensing element directly contacts the arc surface, and the first conductive via is extended from the front surface to the rear surface. In addition, a manufacturing method of the image sensor is also provided.

Abstract: An image sensor including a substrate and an image sensing element is provided. The substrate has an arc surface. The image sensing element is disposed on the arc surface and curved to fit a contour of the arc surface. The image sensing element has a front surface and a rear surface opposite to each other and has at least one first conductive via. The rear surface of the image sensing element directly contacts the arc surface, and the first conductive via is extended from the front surface to the rear surface. In addition, a manufacturing method of the image sensor is also provided.

Abstract: A miniaturized particulate matter detector that includes a filter and a concentration detector is provided. The filter has a plurality of holes, and the concentration detector is correspondingly disposed under the filter. The concentration detector has a detected area used to detect a concentration of at least one miniaturized particulate matter. A manufacturing method of the filter is also provided.

Abstract: In an embodiment, a miniaturize particulate matter detector includes a filter having a plurality of holes, and a concentration detector correspondingly disposed under the filter. The concentration detector has a detect area used for detecting a concentration of at least one miniaturize particulate matter. A manufacturing method of the filter is also provided.

Abstract: In an embodiment, a miniaturize particulate matter detector includes a filter having a plurality of holes, and a concentration detector correspondingly disposed under the filter. The concentration detector has a detect area used for detecting a concentration of at least one miniaturize particulate matter. A manufacturing method of the filter is also provided.

Abstract: A miniaturized particulate matter detector that includes a filter and a concentration detector is provided. The filter has a plurality of holes, and the concentration detector is correspondingly disposed under the filter. The concentration detector has a detected area used to detect a concentration of at least one miniaturized particulate matter. A manufacturing method of the filter is also provided.

Abstract: This invention provides a capacitor device with a high dielectric constant material and multiple vertical electrode plates. The capacitor devices can be directly fabricated on a wafer with low temperature processes so as to be integrated with active devices formed on the wafer. This invention also forms vertical conducting lines in the capacitor devices using the through-silicon-via technology to facilitate the three-dimensional stacking of the capacitor devices.

Abstract: A fabricating method of packaging structure is provided. First, a capacitive element is formed. Then, a first dielectric layer is formed on a first electronic component by performing a build-up process, an interconnection is formed in the first dielectric layer, and a plurality of contacts are formed on the upper and lower surfaces of the first dielectric layer, wherein the capacitive element is embedded in the first dielectric layer during the fabrication of the interconnection and the capacitive element is electrically connected to the corresponding contacts through the interconnection. A second electronic component is disposed on the first dielectric layer, wherein the second electronic component is electrically connected to the corresponding contacts.

Abstract: This invention provides a capacitor device with a high dielectric constant material and multiple vertical electrode plates. The capacitor devices can be directly fabricated on a wafer with low temperature processes so as to be integrated with active devices formed on the wafer. This invention also forms vertical conducting lines in the capacitor devices using the through-silicon-via technology to facilitate the three-dimensional stacking of the capacitor devices.

Abstract: A fabricating method of packaging structure is provided. First, a capacitive element is formed. Then, a first dielectric layer is formed on a first electronic component by performing a build-up process, an interconnection is formed in the first dielectric layer, and a plurality of contacts are formed on the upper and lower surfaces of the first dielectric layer, wherein the capacitive element is embedded in the first dielectric layer during the fabrication of the interconnection and the capacitive element is electrically connected to the corresponding contacts through the interconnection. A second electronic component is disposed on the first dielectric layer, wherein the second electronic component is electrically connected to the corresponding contacts.

Abstract: This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor buried in the insulating layer. A plurality of solder bumps is formed on a backside of the image sensor module so that the module can be directly assembled onto a circuit board. The image sensor module of this invention is characterized by a wafer-level packaging architecture and a three-dimensional die-stacking structure, which reduces electrical connection lengths within the module and thus reduces an area and height of the whole packaged module.

Abstract: A packaging structure including an interposer structure, a first electronic component, and a second electronic component is provided. The interposer structure includes a first dielectric layer, a plurality of contacts, a capacitive element, and an interconnection. The contacts are disposed on the upper and lower surfaces of the first dielectric layer and the capacitive element, which comprises two conductive layers and a second dielectric layer located among the layers, is embedded into the first dielectric layer. And the interconnection is embedded into the first dielectric layer, while the capacitive element electrically connects to the corresponding contacts through the interconnection. The first and the second electronic components are disposed respectively on the upper and bottom sides of the interposer structure and electrically connected to the corresponding contacts.

Abstract: The present invention further provides a chip package process, which includes providing a substrate, disposing a chip on the substrate and forming a buffering compound on the substrate and the chip, wherein the buffering compound covers the chip. The present invention further provides another chip package process, which includes providing a substrate, forming a buffering compound on the substrate and disposing a chip in the buffering compound.

Abstract: This invention provides an image sensor module with a three-dimensional die-stacking structure. By filling a conductive material into through silicon vias within at least one image sensor die, and into via holes within an insulating layer, vertical electrical connections are formed between the image sensor die and an image processor buried in the insulating layer. A plurality of solder bumps is formed on a backside of the image sensor module so that the module can be directly assembled onto a circuit board. The image sensor module of this invention is characterized by a wafer-level packaging architecture and a three-dimensional die-stacking structure, which reduces electrical connection lengths within the module and thus reduces an area and height of the whole packaged module.

Abstract: A packaging structure including an interposer structure, a first electronic component, and a second electronic component is provided. The interposer structure includes a first dielectric layer, a plurality of contacts, a capacitive element, and an interconnection. The contacts are disposed on the upper and lower surfaces of the first dielectric layer and the capacitive element, which comprises two conductive layers and a second dielectric layer located among the layers, is embedded into the first dielectric layer. And the interconnection is embedded into the first dielectric layer, while the capacitive element electrically connects to the corresponding contacts through the interconnection. The first and the second electronic components are disposed respectively on the upper and bottom sides of the interposer structure and electrically connected to the corresponding contacts.

Abstract: An SMD LED package with superior thermal dissipation capability is provided. The SMD LED package comprises a supporting block with circuit patterns and at least one LED attached to the supporting block. Wherein, circuit patterns of holes/vias, insulating layers, and conducting traces/pads are formed on and in the supporting block. The SMD LED packages can be further assembled to form a light module that allows emitted lights to travel in parallel with the mounting surface. The SMD manufacturing process is a mature production process and thus easy for mass production. Single or plural LED chips are mounted on a thermal conducting block that is disposed with patterns of conducting traces/pads and isolating dielectric layers. The side emitting characteristics of the present invention offers the advantage of reflecting and mixing the emitted lights to meet the desired chromaticity.

Abstract: The present invention provides a chip package structure, which includes a chip and a buffering compound, wherein the chip has an active surface, a back surface opposite to the active surface and a plurality of side surfaces joining the active surface and the back surface. The buffering compound is disposed at least on the active surface and the back surface, and the buffering compound possesses Young's modulus between 1 MPa and 1 GPa. The buffering compound contributes to reduce the negative effect of thermal stresses and accordingly advance reliability of the chip package structure. In addition, the present invention further provides a chip package process and based on the same reason the process is able to achieve a better production yield by forming a buffering compound surrounding the chip.

Abstract: An SMD LED package with superior thermal dissipation capability is provided. The SMD LED package comprises a supporting block with circuit patterns and at least one LED attached to the supporting block. Wherein, circuit patterns of holes/vias, insulating layers, and conducting traces/pads are formed on and in the supporting block. The SMD LED packages can be further assembled to from a light module that allows emitted lights to travel in parallel with the mounting surface. The SMD manufacturing process is a mature production process and thus easy for mass production. Single or plural LED chips are mounted on a thermal conducting block that is disposed with patterns of conducting traces/pads and isolating dielectric layers. The side emitting characteristics of the present invention offers the advantage of reflecting and mixing the emitted lights to meet the desired chromaticity.