Patents by Inventor Chia Wen Liu

Chia Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150236092
    Abstract: A semiconductor device with multi-level work function and multi-valued channel doping is provided. The semiconductor device comprises a nanowire structure and a gate region. The nanowire structure is formed as a channel between a source region and a drain region. The nanowire structure has a first doped channel section joined with a second doped channel section. The first doped channel section is coupled to the source region and has a doping concentration greater than the doping concentration of the second doped channel section. The second doped channel section is coupled to the drain region. The gate region is formed around the junction at which the first doped section and the second doped section are joined. The gate region has a first work function gate section joined with a second work function gate section. The first work function gate section is located adjacent to the source region and has a work function greater than the work function of the second work function gate section.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 20, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: TSUNG-HSING YU, YEH HSU, CHIA-WEN LIU, JEAN-PIERRE COLINGE
  • Publication number: 20150236086
    Abstract: A semiconductor structure is provided comprising a vertical channel structure extending from a substrate and formed as a channel between a source region and a drain region. The semiconductor structure further comprises a metal gate that surrounds a portion of the vertical channel structure. The metal gate has a gate length. The metal gate has a first gate section with a first workfunction and a first thickness. The metal gate also has a second gate section with a second workfunction and a second thickness. The first thickness level is different from the second thickness level and the sum of the first thickness level and the second thickness level is equal to the gate length. The ratio of the first thickness level to the second thickness level for the gate length was chosen to achieve a threshold voltage level for the semiconductor device.
    Type: Application
    Filed: August 27, 2014
    Publication date: August 20, 2015
    Inventors: JEAN-PIERRE COLINGE, CHIA-WEN LIU, WEI-HAO WU, CHIH-HAO WANG, CARLOS H. DIAZ
  • Publication number: 20150228775
    Abstract: A semiconductor device having a channel formed from a nanowire with a multi-dimensional diameter is provided. The semiconductor device comprises a drain region formed on a semiconductor substrate. The semiconductor device further comprises a nanowire structure formed between a source region and the drain region. The nanowire structure has a first diameter section joined with a second diameter section. The first diameter section is coupled to the drain region and has a diameter greater than the diameter of the second diameter section. The second diameter section is coupled to the source region. The semiconductor device further comprises a gate region formed around the junction at which the first diameter section and the second diameter section are joined.
    Type: Application
    Filed: February 10, 2014
    Publication date: August 13, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: TSUNG-HSING YU, CHIA-WEN LIU, YEH HSU, JEAN-PIERRE COLINGE
  • Publication number: 20150200296
    Abstract: The present disclosure relates to a method of forming a transistor device having a carbon implantation region that provides for a low variation of voltage threshold, and an associated apparatus. The method is performed by forming a well region within a semiconductor substrate. The semiconductor substrate is selectively etched to form a recess within the well region. After formation of the recess, a carbon implantation is selectively performed to form a carbon implantation region within the semiconductor substrate at a position underlying the recess. An epitaxial growth is then performed to form one or more epitaxial layers within the recess at a position overlying the carbon implantation region. Source and drain regions are subsequently formed within the semiconductor substrate such that a channel region, comprising the one or more epitaxial layers, separates the source/drains from one another.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsing Yu, Chia-Wen Liu, Yeh Hsu, Shih-Syuan Huang, Ken-Ichi Goto, Zhiqiang Wu
  • Publication number: 20150200272
    Abstract: The disclosure provides a method of forming a transistor. In this method, a dummy gate structure is formed over a semiconductor substrate. Source/drain regions are then formed in the semiconductor substrate such that a channel region, which is arranged under the dummy gate structure in the semiconductor substrate, separates the source/drains from one another. After the source/drain regions have been formed, the dummy gate structure is removed. After the dummy gate structure has been removed, a surface region of the channel region is removed to form a channel region recess. A replacement channel region is then epitaxially grown in the channel region recess.
    Type: Application
    Filed: January 16, 2014
    Publication date: July 16, 2015
    Inventors: Chia-Wen Liu, Tsung-Hsing Yu, Wei-Hao Wu, Meikei Ieong, Ken-Ichi Goto, Zhiqiang Wu
  • Publication number: 20150194485
    Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.
    Type: Application
    Filed: March 18, 2015
    Publication date: July 9, 2015
    Inventors: Mahaveer Sathaiya DHANYAKUMAR, Wei-Hao WU, Tsung-Hsing YU, Chia-Wen LIU, Tzer-Min SHEN, Ken-Ichi GOTO, Zhiqiang WU
  • Patent number: 9000526
    Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahaveer Sathaiya Dhanyakumar, Wei-Hao Wu, Tsung-Hsing Yu, Chia-Wen Liu, Tzer-Min Shen, Ken-Ichi Goto, Zhiqiang Wu
  • Patent number: 8993424
    Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wen Liu, Tsung-Hsing Yu, Dhanyakumar Mahaveer Sathaiya, Wei-Hao Wu, Ken-Ichi Goto, Tzer-Min Shen, Zhiqiang Wu
  • Publication number: 20150076596
    Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Tsung-Hsing Yu, Yeh Hsu, Chia-Wen Liu, Carlos H. Diaz
  • Publication number: 20130113041
    Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 9, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wen LIU, Tsung-Hsing Yu, Dhanyakumar Mahaveer Sathaiya, Wei-Hao Wu, Ken-Ichi Goto, Tzer-Min Shen, Zhiqiang Wu
  • Publication number: 20130113047
    Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.
    Type: Application
    Filed: November 3, 2011
    Publication date: May 9, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahaveer Sathaiya Dhanyakumar, Wei-Hao Wu, Tsung-Hsing Yu, Chia-Wen Liu, Tzer-Min Shen, Ken-Ichi Goto, Zhiqiang Wu
  • Publication number: 20090169632
    Abstract: A sustained release composition comprising a polymer and manufacturing method thereof. The sustained release composition comprises a polymer, a bioactive agent, and a release rate determined agent, wherein the release rate determined agent is dispersed in the sustained release composition to control the release rate of the bioactive agent. The method comprises providing an oil phase comprising a bioactive agent, a polymer, and a release rate determined agent; providing an aqueous phase comprising a surfactant; mixing the oil phase with the aqueous phase to form the sustained release composition having a controlled release effect.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jui-Mei Lu, Chia-Wen Liu, Po Hong Lai, John Jiang Hann Lin, Chiao Pin Li, Sung En Chen, Yo Wen Lo, Ming-Thau Sheu, Min-Ying Lin
  • Patent number: 6557320
    Abstract: A the compact disk packing machine includes a base having a box providing device for move empty boxes to a box opening device which opens the empty boxes one by one. A transferring device transfers the opened boxes to a disk providing device and a disk positioning device to put a compact disk in each of the opening boxes. A sheet putting device puts a sheet of commercial in the open boxes and a closing device closes the boxes. The boxes having a compact disk and a sheet of commercial are transferred to a collection device and piled up.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: May 6, 2003
    Inventors: Chen Hsien Chang, Chia Wen Liu, Mao Lung Chien, Ching Chuan Kuo
  • Publication number: 20030041558
    Abstract: A the compact disk packing machine includes a base having a box providing device for move empty boxes to a box opening device which opens the empty boxes one by one. A transferring device transfers the opened boxes to a disk providing device and a disk positioning device to put a compact disk in each of the opening boxes. A sheet putting device puts a sheet of commercial in the open boxes and a closing device closes the boxes. The boxes having a compact disk and a sheet of commercial are transferred to a collection device and piled up.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 6, 2003
    Inventors: Chen Hsien Chang, Chia Wen Liu, Mao Lung Chien, Ching Chuan Kuo
  • Patent number: 6381922
    Abstract: The present invention mainly relates to a transverse displacement mechanism for a compact disc packaging machine includes a working table, an intermittent driving member, a motor, a rocking lever set, and a plurality of transverse displacement frames. The rocking lever set includes two parallel front curved rocking levers, two parallel rear curved rocking levers, two triangular first rotary blocks, two L-shaped second rotary blocks, and two parallel inner curved rocking levers. In operation, the front curved rocking levers, the rear curved rocking levers, and the inner curved rocking levers co-operate with each other to form an eddy state during operation. In such a manner, most of the components of the rocking lever set are hidden in the working table so that the operation of the rocking lever set can be mainly performed in the working table mainly, thereby greatly saving the space of the transverse displacement mechanism for a compact disc packaging machine.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: May 7, 2002
    Inventors: Chen Hsien Chang, Chia Wen Liu, Mao Lung Chien